parent
ab59db3c80
commit
703cf2116b
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@ -6,6 +6,12 @@
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* alias.c (rtx_equal_for_memref_p): VALUEs are only identical
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if their CSELIB_VAL_PTRs are.
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* config/ia64/ia64.c (struct spill_fill_data): New member prev_insn.
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(setup_spill_pointers): Initialize it.
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(spill_restore_mem): Set it.
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(do_spill, do_restore): Use it to add REG_INC note.
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* config/ia64/ia64.md (movti_internal): Add REG_INC notes as needed.
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2001-08-04 Hans-Peter Nilsson <hp@bitrange.com>
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* config/sh/sh.c (sh_asm_named_section): Fix typo in align
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@ -1621,6 +1621,7 @@ struct spill_fill_data
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rtx init_reg[2]; /* initial base register */
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rtx iter_reg[2]; /* the iterator registers */
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rtx *prev_addr[2]; /* address of last memory use */
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rtx prev_insn[2]; /* the insn corresponding to prev_addr */
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HOST_WIDE_INT prev_off[2]; /* last offset */
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int n_iter; /* number of iterators in use */
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int next_iter; /* next iterator to use */
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@ -1642,6 +1643,8 @@ setup_spill_pointers (n_spills, init_reg, cfa_off)
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spill_fill_data.init_reg[1] = init_reg;
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spill_fill_data.prev_addr[0] = NULL;
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spill_fill_data.prev_addr[1] = NULL;
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spill_fill_data.prev_insn[0] = NULL;
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spill_fill_data.prev_insn[1] = NULL;
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spill_fill_data.prev_off[0] = cfa_off;
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spill_fill_data.prev_off[1] = cfa_off;
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spill_fill_data.next_iter = 0;
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@ -1675,11 +1678,16 @@ spill_restore_mem (reg, cfa_off)
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if (spill_fill_data.prev_addr[iter])
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{
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if (CONST_OK_FOR_N (disp))
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{
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*spill_fill_data.prev_addr[iter]
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= gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
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gen_rtx_PLUS (DImode,
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spill_fill_data.iter_reg[iter],
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disp_rtx));
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REG_NOTES (spill_fill_data.prev_insn[iter])
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= gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
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REG_NOTES (spill_fill_data.prev_insn[iter]));
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}
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else
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{
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/* ??? Could use register post_modify for loads. */
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@ -1769,10 +1777,12 @@ do_spill (move_fn, reg, cfa_off, frame_reg)
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rtx reg, frame_reg;
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HOST_WIDE_INT cfa_off;
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{
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int iter = spill_fill_data.next_iter;
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rtx mem, insn;
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mem = spill_restore_mem (reg, cfa_off);
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insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
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spill_fill_data.prev_insn[iter] = insn;
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if (frame_reg)
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{
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@ -1812,8 +1822,12 @@ do_restore (move_fn, reg, cfa_off)
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rtx reg;
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HOST_WIDE_INT cfa_off;
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{
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emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
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int iter = spill_fill_data.next_iter;
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rtx insn;
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insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
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GEN_INT (cfa_off)));
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spill_fill_data.prev_insn[iter] = insn;
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}
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/* Wrapper functions that discards the CONST_INT spill offset. These
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@ -532,7 +532,7 @@
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[(const_int 0)]
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"
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{
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rtx adj1, adj2, in[2], out[2];
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rtx adj1, adj2, in[2], out[2], insn;
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int first;
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adj1 = ia64_split_timode (in, operands[1], operands[2]);
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emit_insn (adj1);
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if (adj2)
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emit_insn (adj2);
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emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
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emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
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if (GET_CODE (out[first]) == MEM
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&& GET_CODE (XEXP (out[first], 0)) == POST_MODIFY)
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REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
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XEXP (XEXP (out[first], 0), 0),
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REG_NOTES (insn));
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
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if (GET_CODE (out[!first]) == MEM
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&& GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY)
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REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
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XEXP (XEXP (out[!first], 0), 0),
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REG_NOTES (insn));
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DONE;
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}"
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[(set_attr "itanium_class" "unknown")
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Reference in New Issue