MSP430: Simplify and extend shift instruction patterns
The implementation of define_expand and define_insn patterns to handle shifts in the MSP430 backend is inconsistent, resulting in missed opportunities to make best use of the architecture's features. There's now a single define_expand used as the entry point for all valid shifts, and the decision to either use a helper function to perform the shift (often required for the 430 ISA), or fall through to the define_insn patterns can be made from that expander function. Shifts by a constant amount have been grouped into one define_insn for each type of shift, instead of having different define_insn patterns for shifts by different amounts. A new target option "-mmax-inline-shift=" has been added to allow tuning of the number of shift instructions to emit inline, instead of using a library helper function. gcc/ChangeLog: * config/msp430/constraints.md (K): Change unused constraint to constraint to a const_int between 1 and 19. (P): New constraint. * config/msp430/msp430-protos.h (msp430x_logical_shift_right): Remove. (msp430_expand_shift): New. (msp430_output_asm_shift_insns): New. * config/msp430/msp430.c (msp430_rtx_costs): Remove shift costs. (CSH): Remove. (msp430_expand_helper): Remove hard-coded generation of some inline shift insns. (use_helper_for_const_shift): New. (msp430_expand_shift): New. (msp430_output_asm_shift_insns): New. (msp430_print_operand): Add new 'W' operand selector. (msp430x_logical_shift_right): Remove. * config/msp430/msp430.md (HPSI): New define_mode_iterator. (HDI): Likewise. (any_shift): New define_code_iterator. (shift_insn): New define_code_attr. Adjust unnamed insn patterns searched for by combine. (ashlhi3): Remove. (slli_1): Remove. (430x_shift_left): Remove. (slll_1): Remove. (slll_2): Remove. (ashlsi3): Remove. (ashldi3): Remove. (ashrhi3): Remove. (srai_1): Remove. (430x_arithmetic_shift_right): Remove. (srap_1): Remove. (srap_2): Remove. (sral_1): Remove. (sral_2): Remove. (ashrsi3): Remove. (ashrdi3): Remove. (lshrhi3): Remove. (srli_1): Remove. (430x_logical_shift_right): Remove. (srlp_1): Remove. (srll_1): Remove. (srll_2x): Remove. (lshrsi3): Remove. (lshrdi3): Remove. (<shift_insn><mode>3): New define_expand. (<shift_insn>hi3_430): New define_insn. (<shift_insn>si3_const): Likewise. (ashl<mode>3_430x): Likewise. (ashr<mode>3_430x): Likewise. (lshr<mode>3_430x): Likewise. (*bitbranch<mode>4_z): Replace renamed predicate msp430_bitpos with const_0_to_15_operand. * config/msp430/msp430.opt: New option -mmax-inline-shift=. * config/msp430/predicates.md (const_1_to_8_operand): New predicate. (const_0_to_15_operand): Rename msp430_bitpos predicate. (const_1_to_19_operand): New predicate. * doc/invoke.texi: Document -mmax-inline-shift=. libgcc/ChangeLog: * config/msp430/slli.S (__gnu_mspabi_sllp): New. * config/msp430/srai.S (__gnu_mspabi_srap): New. * config/msp430/srli.S (__gnu_mspabi_srlp): New. gcc/testsuite/ChangeLog: * gcc.target/msp430/emulate-srli.c: Fix expected assembler text. * gcc.target/msp430/max-inline-shift-430-no-opt.c: New test. * gcc.target/msp430/max-inline-shift-430.c: New test. * gcc.target/msp430/max-inline-shift-430x.c: New test.
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@ -25,15 +25,16 @@
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"Register R13.")
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(define_constraint "K"
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"Integer constant 1."
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"Integer constant 1-19."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 1, 1)")))
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(match_test "IN_RANGE (ival, 1, 19)")))
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(define_constraint "L"
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"Integer constant -1^20..1^19."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, HOST_WIDE_INT_M1U << 20, 1 << 19)")))
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;; Valid shift amount for RRUM, RRAM, RLAM, RRCM.
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(define_constraint "M"
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"Integer constant 1-4."
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(and (match_code "const_int")
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@ -49,6 +50,11 @@
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 256, 65535)")))
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(define_constraint "P"
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"Integer constant 1-16."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 1, 16)")))
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;; We do not allow arbitrary constants, eg symbols or labels,
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;; because their address may be above the 16-bit address limit
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;; supported by the offset used in the MOVA instruction.
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@ -35,7 +35,6 @@ rtx msp430_incoming_return_addr_rtx (void);
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void msp430_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
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int msp430_initial_elimination_offset (int, int);
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bool msp430_is_interrupt_func (void);
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const char * msp430x_logical_shift_right (rtx);
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const char * msp430_mcu_name (void);
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void msp430_output_aligned_decl_common (FILE *, const tree, const char *,
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unsigned HOST_WIDE_INT, unsigned,
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@ -51,4 +50,9 @@ bool msp430_use_f5_series_hwmult (void);
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bool msp430_has_hwmult (void);
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bool msp430_op_not_in_high_mem (rtx op);
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#ifdef RTX_CODE
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int msp430_expand_shift (enum rtx_code code, machine_mode mode, rtx *operands);
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const char * msp430_output_asm_shift_insns (enum rtx_code code, machine_mode mode, rtx *operands);
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#endif
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#endif /* GCC_MSP430_PROTOS_H */
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@ -1064,15 +1064,6 @@ static bool msp430_rtx_costs (rtx x ATTRIBUTE_UNUSED,
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return true;
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}
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break;
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case ASHIFT:
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case ASHIFTRT:
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case LSHIFTRT:
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if (!msp430x)
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{
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*total = COSTS_N_INSNS (100);
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return true;
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}
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break;
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}
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return false;
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}
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@ -2674,32 +2665,6 @@ msp430_init_dwarf_reg_sizes_extra (tree address)
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}
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}
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/* This is a list of MD patterns that implement fixed-count shifts. */
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static struct
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{
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const char *name;
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int count;
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int need_430x;
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rtx (*genfunc)(rtx,rtx);
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}
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const_shift_helpers[] =
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{
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#define CSH(N,C,X,G) { "__mspabi_" N, C, X, gen_##G }
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CSH ("slli", 1, 1, slli_1),
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CSH ("slll", 1, 1, slll_1),
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CSH ("slll", 2, 1, slll_2),
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CSH ("srai", 1, 0, srai_1),
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CSH ("sral", 1, 0, sral_1),
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CSH ("sral", 2, 0, sral_2),
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CSH ("srll", 1, 0, srll_1),
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CSH ("srll", 2, 1, srll_2x),
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{ 0, 0, 0, 0 }
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#undef CSH
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};
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/* The MSP430 ABI defines a number of helper functions that should be
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used for, for example, 32-bit shifts. This function is called to
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emit such a function, using the table above to optimize some
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@ -2716,31 +2681,12 @@ msp430_expand_helper (rtx *operands, const char *helper_name,
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machine_mode arg0mode = GET_MODE (operands[0]);
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machine_mode arg1mode = GET_MODE (operands[1]);
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machine_mode arg2mode = GET_MODE (operands[2]);
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int have_430x = msp430x ? 1 : 0;
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int expand_mpy = strncmp (helper_name, "__mspabi_mpy",
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sizeof ("__mspabi_mpy") - 1) == 0;
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/* This function has been used incorrectly if CONST_VARIANTS is TRUE for a
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hwmpy function. */
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gcc_assert (!(expand_mpy && const_variants));
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/* Emit size-optimal insns for small shifts we can easily do inline. */
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if (CONST_INT_P (operands[2]) && !expand_mpy)
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{
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int i;
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for (i=0; const_shift_helpers[i].name; i++)
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{
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if (const_shift_helpers[i].need_430x <= have_430x
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&& strcmp (helper_name, const_shift_helpers[i].name) == 0
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&& INTVAL (operands[2]) == const_shift_helpers[i].count)
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{
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emit_insn (const_shift_helpers[i].genfunc (operands[0],
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operands[1]));
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return;
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}
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}
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}
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if (arg1mode != VOIDmode && arg2mode != VOIDmode)
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/* Modes of arguments must be equal if not constants. */
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gcc_assert (arg1mode == arg2mode);
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@ -2835,6 +2781,190 @@ msp430_expand_helper (rtx *operands, const char *helper_name,
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gen_rtx_REG (arg0mode, 12));
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}
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/* Return TRUE if the helper function should be used and FALSE if the shifts
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insns should be emitted inline. */
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static bool
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use_helper_for_const_shift (enum rtx_code code, machine_mode mode,
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HOST_WIDE_INT amt)
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{
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const int default_inline_shift = 4;
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/* We initialize the option to 65 so we know if the user set it or not. */
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int user_set_max_inline = (msp430_max_inline_shift == 65 ? 0 : 1);
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int max_inline = (user_set_max_inline ? msp430_max_inline_shift
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: default_inline_shift);
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/* 32-bit shifts are roughly twice as costly as 16-bit shifts so we adjust
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the heuristic accordingly. */
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int max_inline_32 = max_inline / 2;
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/* Don't use helpers for these modes on 430X, when optimizing for speed, or
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when emitting a small number of insns. */
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if ((mode == E_QImode || mode == E_HImode || mode == E_PSImode)
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&& (msp430x
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/* If the user set max_inline then we always obey that number.
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Otherwise we always emit the shifts inline at -O2 and above. */
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|| amt <= max_inline
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|| (!user_set_max_inline
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&& (optimize >= 2 && !optimize_size))))
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return false;
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/* 430 and 430X codegen for SImode shifts is the same.
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Set a hard limit of 15 for the number of shifts that will be emitted
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inline by default, even at -O2 and above, to prevent code size
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explosion. */
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if (mode == E_SImode
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&& (amt <= max_inline_32
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|| (!user_set_max_inline
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&& (optimize >= 2 && !optimize_size)
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&& amt <= 15)))
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return false;
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return true;
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}
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/* For shift operations which will use an mspabi helper function, setup the
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call to msp430_expand helper. Return 1 to indicate we have finished with
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this insn and invoke "DONE".
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Otherwise return 0 to indicate the insn should fallthrough.
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Never FAIL. */
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int
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msp430_expand_shift (enum rtx_code code, machine_mode mode, rtx *operands)
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{
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/* Always use the helper function when the shift amount is not a
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constant. */
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if (!CONST_INT_P (operands[2])
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|| mode == E_DImode
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|| use_helper_for_const_shift (code, mode, INTVAL (operands[2])))
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{
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const char *helper_name = NULL;
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/* The const variants of mspabi shifts have significantly larger code
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size than the generic version, so use the generic version if
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optimizing for size. */
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bool const_variant = !optimize_size;
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switch (mode)
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{
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case E_HImode:
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helper_name = (code == ASHIFT ? "__mspabi_slli" :
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(code == ASHIFTRT ? "__mspabi_srai" :
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(code == LSHIFTRT ? "__mspabi_srli" :
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NULL)));
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break;
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case E_PSImode:
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helper_name = (code == ASHIFT ? "__gnu_mspabi_sllp" :
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(code == ASHIFTRT ? "__gnu_mspabi_srap" :
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(code == LSHIFTRT ? "__gnu_mspabi_srlp" :
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NULL)));
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/* No const variant for PSImode shifts FIXME. */
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const_variant = false;
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break;
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case E_SImode:
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helper_name = (code == ASHIFT ? "__mspabi_slll" :
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(code == ASHIFTRT ? "__mspabi_sral" :
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(code == LSHIFTRT ? "__mspabi_srll" :
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NULL)));
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break;
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case E_DImode:
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helper_name = (code == ASHIFT ? "__mspabi_sllll" :
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(code == ASHIFTRT ? "__mspabi_srall" :
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(code == LSHIFTRT ? "__mspabi_srlll" :
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NULL)));
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/* No const variant for DImode shifts. */
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const_variant = false;
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break;
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default:
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gcc_unreachable ();
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break;
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}
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gcc_assert (helper_name);
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msp430_expand_helper (operands, helper_name, const_variant);
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return 1;
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}
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/* When returning 0, there must be an insn to match the RTL pattern
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otherwise there will be an unrecognizeable insn. */
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return 0;
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}
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/* Helper function to emit a sequence of shift instructions. The amount of
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shift instructions to emit is in OPERANDS[2].
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For 430 we output copies of identical inline shifts for all modes.
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For 430X it is inneficient to do so for any modes except SI and DI, since we
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can make use of R*M insns or RPT with 430X insns, so this function is only
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used for SImode in that case. */
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const char *
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msp430_output_asm_shift_insns (enum rtx_code code, machine_mode mode,
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rtx *operands)
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{
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int i;
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int amt;
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int max_shift = GET_MODE_BITSIZE (mode) - 1;
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gcc_assert (CONST_INT_P (operands[2]));
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amt = INTVAL (operands[2]);
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if (amt == 0 || amt > max_shift)
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{
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switch (code)
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{
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case ASHIFT:
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output_asm_insn ("# ignored undefined behaviour left shift "
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"of %1 by %2", operands);
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break;
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case ASHIFTRT:
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output_asm_insn ("# ignored undefined behaviour arithmetic right "
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"shift of %1 by %2", operands);
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break;
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case LSHIFTRT:
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output_asm_insn ("# ignored undefined behaviour logical right shift "
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"of %1 by %2", operands);
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break;
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default:
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gcc_unreachable ();
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}
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return "";
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}
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if (code == ASHIFT)
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{
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if (!msp430x && mode == HImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("RLA.W\t%0", operands);
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else if (mode == SImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("RLA%X0.W\t%L0 { RLC%X0.W\t%H0", operands);
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else
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/* Catch unhandled cases. */
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gcc_unreachable ();
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}
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else if (code == ASHIFTRT)
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{
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if (!msp430x && mode == HImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("RRA.W\t%0", operands);
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else if (mode == SImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("RRA%X0.W\t%H0 { RRC%X0.W\t%L0", operands);
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else
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gcc_unreachable ();
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}
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else if (code == LSHIFTRT)
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{
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if (!msp430x && mode == HImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("CLRC { RRC.W\t%0", operands);
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else if (mode == SImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("CLRC { RRC%X0.W\t%H0 { RRC%X0.W\t%L0", operands);
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/* FIXME: Why doesn't "RRUX.W\t%H0 { RRC%X0.W\t%L0" work for msp430x?
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It causes execution timeouts e.g. pr41963.c. */
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#if 0
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else if (msp430x && mode == SImode)
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for (i = 0; i < amt; i++)
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output_asm_insn ("RRUX.W\t%H0 { RRC%X0.W\t%L0", operands);
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#endif
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else
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gcc_unreachable ();
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}
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return "";
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}
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/* Called by cbranch<mode>4 to coerce operands into usable forms. */
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void
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msp430_fixup_compare_operands (machine_mode my_mode, rtx * operands)
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@ -3368,6 +3498,7 @@ msp430_op_not_in_high_mem (rtx op)
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O offset of the top of the stack
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Q like X but generates an A postfix
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R inverse of condition code, unsigned.
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W value - 16
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X X instruction postfix in large mode
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Y value - 4
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Z value - 1
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@ -3394,6 +3525,11 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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/* Print the constant value, less four. */
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fprintf (file, "#%ld", INTVAL (op) - 4);
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return;
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case 'W':
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gcc_assert (CONST_INT_P (op));
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/* Print the constant value, less 16. */
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fprintf (file, "#%ld", INTVAL (op) - 16);
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return;
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case 'I':
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if (GET_CODE (op) == CONST_INT)
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{
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@ -3711,34 +3847,6 @@ msp430x_extendhisi (rtx * operands)
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return "MOV.W\t%1, %L0 { MOV.W\t%1, %H0 { RPT\t#15 { RRAX.W\t%H0";
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}
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/* Likewise for logical right shifts. */
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const char *
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msp430x_logical_shift_right (rtx amount)
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{
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/* The MSP430X's logical right shift instruction - RRUM - does
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not use an extension word, so we cannot encode a repeat count.
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Try various alternatives to work around this. If the count
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is in a register we are stuck, hence the assert. */
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gcc_assert (CONST_INT_P (amount));
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if (INTVAL (amount) <= 0
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|| INTVAL (amount) >= 16)
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return "# nop logical shift.";
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if (INTVAL (amount) > 0
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&& INTVAL (amount) < 5)
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return "rrum.w\t%2, %0"; /* Two bytes. */
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if (INTVAL (amount) > 4
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&& INTVAL (amount) < 9)
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return "rrum.w\t#4, %0 { rrum.w\t%Y2, %0 "; /* Four bytes. */
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/* First we logically shift right by one. Now we know
|
||||
that the top bit is zero and we can use the arithmetic
|
||||
right shift instruction to perform the rest of the shift. */
|
||||
return "rrum.w\t#1, %0 { rpt\t%Z2 { rrax.w\t%0"; /* Six bytes. */
|
||||
}
|
||||
|
||||
/* Stop GCC from thinking that it can eliminate (SUBREG:PSI (SI)). */
|
||||
|
||||
#undef TARGET_CAN_CHANGE_MODE_CLASS
|
||||
|
|
|
@ -65,6 +65,15 @@
|
|||
(include "constraints.md")
|
||||
|
||||
(define_mode_iterator QHI [QI HI PSI])
|
||||
(define_mode_iterator HPSI [HI PSI])
|
||||
(define_mode_iterator HDI [HI PSI SI DI])
|
||||
|
||||
;; Mapping of all shift operators
|
||||
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
|
||||
|
||||
;; Base name for define_insn
|
||||
(define_code_attr shift_insn
|
||||
[(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
|
||||
|
||||
;; There are two basic "family" tests we do here:
|
||||
;;
|
||||
|
@ -689,31 +698,42 @@
|
|||
MOV%X1.B\t%1, %0"
|
||||
)
|
||||
|
||||
;; The next three insns emit identical assembly code.
|
||||
;; They take a QImode and shift it in SImode. Only shift counts <= 8
|
||||
;; are handled since that is the simple case where the high 16-bits (i.e. the
|
||||
;; high register) are always 0.
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ashift:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "rm"))
|
||||
(match_operand:HI 2 "immediate_operand" "M")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(ashift:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "0,rm,rm"))
|
||||
(match_operand:HI 2 "const_1_to_8_operand" "M,M,i")))]
|
||||
"msp430x"
|
||||
"MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0"
|
||||
"@
|
||||
RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RPT %2 { RLAX.W %L0 { CLR %H0"
|
||||
)
|
||||
|
||||
;; We are taking a char and shifting it and putting the result in 2 registers.
|
||||
;; the high register will always be for 0 shift counts < 8.
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ashift:SI (zero_extend:SI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0))
|
||||
(match_operand:HI 2 "immediate_operand" "M")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(ashift:SI (zero_extend:SI (subreg:HI (match_operand:QI 1 "general_operand" "0,rm,rm") 0))
|
||||
(match_operand:HI 2 "const_1_to_8_operand" "M,M,i")))]
|
||||
"msp430x"
|
||||
"MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0"
|
||||
"@
|
||||
RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RPT %2 { RLAX.W %L0 { CLR %H0"
|
||||
)
|
||||
|
||||
;; Same as above but with a NOP sign_extend round the subreg
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ashift:SI (zero_extend:SI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0)))
|
||||
(match_operand:HI 2 "immediate_operand" "M")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(ashift:SI (zero_extend:SI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "0,rm,rm") 0)))
|
||||
(match_operand:HI 2 "const_1_to_8_operand" "M,M,i")))]
|
||||
"msp430x"
|
||||
"MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0"
|
||||
"@
|
||||
RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0
|
||||
MOV%X1.B %1, %L0 { RPT %2 { RLAX.W %L0 { CLR %H0"
|
||||
)
|
||||
|
||||
(define_insn ""
|
||||
|
@ -724,11 +744,14 @@
|
|||
)
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r")
|
||||
(ashift:PSI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0))
|
||||
(match_operand:HI 2 "immediate_operand" "M")))]
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r,r,r")
|
||||
(ashift:PSI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "0,rm,rm") 0))
|
||||
(match_operand:HI 2 "const_1_to_19_operand" "M,M,i")))]
|
||||
"msp430x"
|
||||
"MOV%X1.B %1, %0 { RLAM.W %2, %0"
|
||||
"@
|
||||
RLAM.W %2, %0
|
||||
MOV%X1.B %1, %0 { RLAM.W %2, %0
|
||||
MOV%X1.B %1, %0 { RPT %2 { RLAX.A %0"
|
||||
)
|
||||
;; END msp430 pointer manipulation combine insn patterns
|
||||
|
||||
|
@ -840,287 +863,75 @@
|
|||
;; Note - we ignore shift counts of less than one or more than 15.
|
||||
;; This is permitted by the ISO C99 standard as such shifts result
|
||||
;; in "undefined" behavior. [6.5.7 (3)]
|
||||
;;
|
||||
;; We avoid emitting insns in msp430_expand_shift, since we would have to handle
|
||||
;; many extra cases such as op0 != op1, or, op0 or op1 in memory. Instead we
|
||||
;; let reload coerce op0 and op1 into the same register.
|
||||
|
||||
;; signed A << C
|
||||
|
||||
(define_expand "ashlhi3"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashift:HI (match_operand:HI 1 "general_operand")
|
||||
(match_operand:HI 2 "general_operand")))]
|
||||
(define_expand "<shift_insn><mode>3"
|
||||
[(set (match_operand:HDI 0 "msp430_general_dst_nonv_operand")
|
||||
(any_shift:HDI (match_operand:HDI 1 "general_operand")
|
||||
(match_operand:HDI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
if ((GET_CODE (operands[1]) == SUBREG
|
||||
&& REG_P (XEXP (operands[1], 0)))
|
||||
|| MEM_P (operands[1]))
|
||||
operands[1] = force_reg (HImode, operands[1]);
|
||||
if (msp430x
|
||||
&& REG_P (operands[0])
|
||||
&& REG_P (operands[1])
|
||||
&& CONST_INT_P (operands[2]))
|
||||
emit_insn (gen_430x_shift_left (operands[0], operands[1], operands[2]));
|
||||
else if (CONST_INT_P (operands[2])
|
||||
&& INTVAL (operands[2]) == 1)
|
||||
emit_insn (gen_slli_1 (operands[0], operands[1]));
|
||||
else
|
||||
/* The const variants of mspabi shifts have larger code size than the
|
||||
generic version, so use the generic version if optimizing for
|
||||
size. */
|
||||
msp430_expand_helper (operands, \"__mspabi_slli\", !optimize_size);
|
||||
DONE;
|
||||
if (msp430_expand_shift (<CODE>, <MODE>mode, operands))
|
||||
DONE;
|
||||
/* Otherwise, fallthrough. */
|
||||
}
|
||||
)
|
||||
|
||||
(define_insn "slli_1"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(ashift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"RLA%X0.W\t%0" ;; Note - this is a macro for ADD
|
||||
;; All 430 HImode constant shifts
|
||||
(define_insn "<shift_insn>hi3_430"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(any_shift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:HI 2 "const_int_operand" "n")))]
|
||||
"!msp430x"
|
||||
"* return msp430_output_asm_shift_insns (<CODE>, HImode, operands);"
|
||||
)
|
||||
|
||||
(define_insn "430x_shift_left"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(ashift:HI (match_operand:HI 1 "register_operand" "0")
|
||||
(match_operand 2 "immediate_operand" "n")))]
|
||||
;; All 430 and 430X SImode constant shifts
|
||||
(define_insn "<shift_insn>si3_const"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(any_shift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"* return msp430_output_asm_shift_insns (<CODE>, SImode, operands);"
|
||||
)
|
||||
|
||||
(define_insn "ashl<mode>3_430x"
|
||||
[(set (match_operand:HPSI 0 "msp430_general_dst_nonv_operand" "=r,r,r,r")
|
||||
(ashift:HPSI (match_operand:HPSI 1 "general_operand" "0 ,0,0,0")
|
||||
(match_operand:HPSI 2 "const_int_operand" "M ,P,K,i")))]
|
||||
"msp430x"
|
||||
"*
|
||||
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 5)
|
||||
return \"RLAM.W\t%2, %0\";
|
||||
else if (INTVAL (operands[2]) >= 5 && INTVAL (operands[2]) < 16)
|
||||
return \"RPT\t%2 { RLAX.W\t%0\";
|
||||
return \"# nop left shift\";
|
||||
"
|
||||
"@
|
||||
RLAM%b0\t%2, %0
|
||||
RPT\t%2 { RLAX%b0\t%0
|
||||
RPT\t#16 { RLAX%b0\t%0 { RPT\t%W2 { RLAX%b0\t%0
|
||||
# undefined behavior left shift of %1 by %2"
|
||||
)
|
||||
|
||||
(define_insn "slll_1"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(ashift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"RLA%X0.W\t%L0 { RLC%X0.W\t%H0"
|
||||
)
|
||||
|
||||
(define_insn "slll_2"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(ashift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 2)))]
|
||||
""
|
||||
"RLA%X0.W\t%L0 { RLC%X0.W\t%H0 { RLA%X0.W\t%L0 { RLC%X0.W\t%H0"
|
||||
)
|
||||
|
||||
(define_expand "ashlsi3"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashift:SI (match_operand:SI 1 "general_operand")
|
||||
(match_operand:SI 2 "general_operand")))]
|
||||
""
|
||||
"msp430_expand_helper (operands, \"__mspabi_slll\", !optimize_size);
|
||||
DONE;"
|
||||
)
|
||||
|
||||
(define_expand "ashldi3"
|
||||
[(set (match_operand:DI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashift:DI (match_operand:DI 1 "general_operand")
|
||||
(match_operand:DI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
/* No const_variant for 64-bit shifts. */
|
||||
msp430_expand_helper (operands, \"__mspabi_sllll\", false);
|
||||
DONE;
|
||||
}
|
||||
)
|
||||
|
||||
;;----------
|
||||
|
||||
;; signed A >> C
|
||||
|
||||
(define_expand "ashrhi3"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashiftrt:HI (match_operand:HI 1 "general_operand")
|
||||
(match_operand:HI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
if ((GET_CODE (operands[1]) == SUBREG
|
||||
&& REG_P (XEXP (operands[1], 0)))
|
||||
|| MEM_P (operands[1]))
|
||||
operands[1] = force_reg (HImode, operands[1]);
|
||||
if (msp430x
|
||||
&& REG_P (operands[0])
|
||||
&& REG_P (operands[1])
|
||||
&& CONST_INT_P (operands[2]))
|
||||
emit_insn (gen_430x_arithmetic_shift_right (operands[0], operands[1], operands[2]));
|
||||
else if (CONST_INT_P (operands[2])
|
||||
&& INTVAL (operands[2]) == 1)
|
||||
emit_insn (gen_srai_1 (operands[0], operands[1]));
|
||||
else
|
||||
msp430_expand_helper (operands, \"__mspabi_srai\", !optimize_size);
|
||||
DONE;
|
||||
}
|
||||
)
|
||||
|
||||
(define_insn "srai_1"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_operand" "=rm")
|
||||
(ashiftrt:HI (match_operand:HI 1 "msp430_general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"RRA%X0.W\t%0"
|
||||
)
|
||||
|
||||
(define_insn "430x_arithmetic_shift_right"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
||||
(match_operand 2 "immediate_operand" "n")))]
|
||||
(define_insn "ashr<mode>3_430x"
|
||||
[(set (match_operand:HPSI 0 "msp430_general_dst_nonv_operand" "=r,r,r,r")
|
||||
(ashiftrt:HPSI (match_operand:HPSI 1 "general_operand" "0,0,0,0")
|
||||
(match_operand:HPSI 2 "const_int_operand" "M,P,K,i")))]
|
||||
"msp430x"
|
||||
"*
|
||||
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 5)
|
||||
return \"RRAM.W\t%2, %0\";
|
||||
else if (INTVAL (operands[2]) >= 5 && INTVAL (operands[2]) < 16)
|
||||
return \"RPT\t%2 { RRAX.W\t%0\";
|
||||
return \"# nop arith right shift\";
|
||||
"
|
||||
"@
|
||||
RRAM%b0\t%2, %0
|
||||
RPT\t%2 { RRAX%b0\t%0
|
||||
RPT\t#16 { RRAX%b0\t%0 { RPT\t%W2 { RRAX%b0\t%0
|
||||
# undefined behavior arithmetic right shift of %1 by %2"
|
||||
)
|
||||
|
||||
(define_insn "srap_1"
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r")
|
||||
(ashiftrt:PSI (match_operand:PSI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
(define_insn "lshr<mode>3_430x"
|
||||
[(set (match_operand:HPSI 0 "msp430_general_dst_nonv_operand" "=r,r,r,r")
|
||||
(lshiftrt:HPSI (match_operand:HPSI 1 "general_operand" "0,0,0,0")
|
||||
(match_operand:HPSI 2 "const_int_operand" "M,P,K,i")))]
|
||||
"msp430x"
|
||||
"RRAM.A #1,%0"
|
||||
)
|
||||
|
||||
(define_insn "srap_2"
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r")
|
||||
(ashiftrt:PSI (match_operand:PSI 1 "general_operand" "0")
|
||||
(const_int 2)))]
|
||||
"msp430x"
|
||||
"RRAM.A #2,%0"
|
||||
)
|
||||
|
||||
(define_insn "sral_1"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"RRA%X0.W\t%H0 { RRC%X0.W\t%L0"
|
||||
)
|
||||
|
||||
(define_insn "sral_2"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 2)))]
|
||||
""
|
||||
"RRA%X0.W\t%H0 { RRC%X0.W\t%L0 { RRA%X0.W\t%H0 { RRC%X0.W\t%L0"
|
||||
)
|
||||
|
||||
(define_expand "ashrsi3"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashiftrt:SI (match_operand:SI 1 "general_operand")
|
||||
(match_operand:SI 2 "general_operand")))]
|
||||
""
|
||||
"msp430_expand_helper (operands, \"__mspabi_sral\", !optimize_size);
|
||||
DONE;"
|
||||
)
|
||||
|
||||
(define_expand "ashrdi3"
|
||||
[(set (match_operand:DI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashift:DI (match_operand:DI 1 "general_operand")
|
||||
(match_operand:DI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
/* No const_variant for 64-bit shifts. */
|
||||
msp430_expand_helper (operands, \"__mspabi_srall\", false);
|
||||
DONE;
|
||||
}
|
||||
)
|
||||
|
||||
;;----------
|
||||
|
||||
;; unsigned A >> C
|
||||
|
||||
(define_expand "lshrhi3"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand")
|
||||
(lshiftrt:HI (match_operand:HI 1 "general_operand")
|
||||
(match_operand:HI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
if ((GET_CODE (operands[1]) == SUBREG
|
||||
&& REG_P (XEXP (operands[1], 0)))
|
||||
|| MEM_P (operands[1]))
|
||||
operands[1] = force_reg (HImode, operands[1]);
|
||||
if (msp430x
|
||||
&& REG_P (operands[0])
|
||||
&& REG_P (operands[1])
|
||||
&& CONST_INT_P (operands[2]))
|
||||
emit_insn (gen_430x_logical_shift_right (operands[0], operands[1], operands[2]));
|
||||
else if (CONST_INT_P (operands[2])
|
||||
&& INTVAL (operands[2]) == 1)
|
||||
emit_insn (gen_srli_1 (operands[0], operands[1]));
|
||||
else
|
||||
msp430_expand_helper (operands, \"__mspabi_srli\", !optimize_size);
|
||||
DONE;
|
||||
}
|
||||
)
|
||||
|
||||
(define_insn "srli_1"
|
||||
[(set (match_operand:HI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"CLRC { RRC%X0.W\t%0"
|
||||
)
|
||||
|
||||
(define_insn "430x_logical_shift_right"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
||||
(match_operand 2 "immediate_operand" "n")))]
|
||||
"msp430x"
|
||||
{
|
||||
return msp430x_logical_shift_right (operands[2]);
|
||||
}
|
||||
)
|
||||
|
||||
(define_insn "srlp_1"
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r")
|
||||
(lshiftrt:PSI (match_operand:PSI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"RRUM.A #1,%0"
|
||||
)
|
||||
|
||||
(define_insn "srll_1"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 1)))]
|
||||
""
|
||||
"CLRC { RRC%X0.W\t%H0 { RRC%X0.W\t%L0"
|
||||
)
|
||||
|
||||
(define_insn "srll_2x"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(const_int 2)))]
|
||||
"msp430x"
|
||||
"RRUX.W\t%H0 { RRC.W\t%L0 { RRUX.W\t%H0 { RRC.W\t%L0"
|
||||
)
|
||||
|
||||
(define_expand "lshrsi3"
|
||||
[(set (match_operand:SI 0 "msp430_general_dst_nonv_operand")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand")
|
||||
(match_operand:SI 2 "general_operand")))]
|
||||
""
|
||||
"msp430_expand_helper (operands, \"__mspabi_srll\", !optimize_size);
|
||||
DONE;"
|
||||
)
|
||||
|
||||
(define_expand "lshrdi3"
|
||||
[(set (match_operand:DI 0 "msp430_general_dst_nonv_operand")
|
||||
(ashift:DI (match_operand:DI 1 "general_operand")
|
||||
(match_operand:DI 2 "general_operand")))]
|
||||
""
|
||||
{
|
||||
/* No const_variant for 64-bit shifts. */
|
||||
msp430_expand_helper (operands, \"__mspabi_srlll\", false);
|
||||
DONE;
|
||||
}
|
||||
"@
|
||||
RRUM%b0\t%2, %0
|
||||
RPT\t%2 { RRUX%b0\t%0
|
||||
RPT\t#16 { RRUX%b0\t%0 { RPT\t%W2 { RRUX%b0\t%0
|
||||
# undefined behavior logical right shift of %1 by %2"
|
||||
)
|
||||
|
||||
;;------------------------------------------------------------
|
||||
|
@ -1427,7 +1238,7 @@
|
|||
[(set (pc) (if_then_else
|
||||
(ne (zero_extract:HI (match_operand:QHI 0 "msp430_general_dst_operand" "rYs,rm")
|
||||
(const_int 1)
|
||||
(match_operand 1 "msp430_bitpos" "i,i"))
|
||||
(match_operand 1 "const_0_to_15_operand" "i,i"))
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))
|
||||
|
@ -1443,7 +1254,7 @@
|
|||
[(set (pc) (if_then_else
|
||||
(eq (zero_extract:HI (match_operand:QHI 0 "msp430_general_dst_operand" "rm")
|
||||
(const_int 1)
|
||||
(match_operand 1 "msp430_bitpos" "i"))
|
||||
(match_operand 1 "const_0_to_15_operand" "i"))
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))
|
||||
|
@ -1457,7 +1268,7 @@
|
|||
[(set (pc) (if_then_else
|
||||
(eq (zero_extract:HI (match_operand:QHI 0 "msp430_general_dst_operand" "rm")
|
||||
(const_int 1)
|
||||
(match_operand 1 "msp430_bitpos" "i"))
|
||||
(match_operand 1 "const_0_to_15_operand" "i"))
|
||||
(const_int 0))
|
||||
(pc)
|
||||
(label_ref (match_operand 2 "" ""))))
|
||||
|
@ -1471,7 +1282,7 @@
|
|||
[(set (pc) (if_then_else
|
||||
(ne (zero_extract:HI (match_operand:QHI 0 "msp430_general_dst_operand" "rm")
|
||||
(const_int 1)
|
||||
(match_operand 1 "msp430_bitpos" "i"))
|
||||
(match_operand 1 "const_0_to_15_operand" "i"))
|
||||
(const_int 0))
|
||||
(pc)
|
||||
(label_ref (match_operand 2 "" ""))))
|
||||
|
|
|
@ -109,3 +109,9 @@ mdevices-csv-loc=
|
|||
Target Joined Var(msp430_devices_csv_loc) RejectNegative Report
|
||||
The path to devices.csv. The GCC driver can normally locate devices.csv itself
|
||||
and pass this option to the compiler, so the user shouldn't need to pass this.
|
||||
|
||||
mmax-inline-shift=
|
||||
Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65) Report
|
||||
For shift operations by a constant amount, which require an individual instruction to shift by one
|
||||
position, set the maximum number of inline shift instructions (maximum value 64) to emit instead of using the corresponding __mspabi helper function.
|
||||
The default value is 4.
|
||||
|
|
|
@ -113,12 +113,21 @@
|
|||
(ior (match_code "reg,mem")
|
||||
(match_operand 0 "immediate_operand"))))
|
||||
|
||||
; TRUE for constants which are bit positions for zero_extract
|
||||
(define_predicate "msp430_bitpos"
|
||||
(define_predicate "const_1_to_8_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test (" INTVAL (op) >= 1
|
||||
&& INTVAL (op) <= 8 "))))
|
||||
|
||||
(define_predicate "const_0_to_15_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test (" INTVAL (op) >= 0
|
||||
&& INTVAL (op) <= 15 "))))
|
||||
|
||||
(define_predicate "const_1_to_19_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test (" INTVAL (op) >= 1
|
||||
&& INTVAL (op) <= 19 "))))
|
||||
|
||||
(define_predicate "msp430_symbol_operand"
|
||||
(match_code "symbol_ref")
|
||||
)
|
||||
|
|
|
@ -1070,7 +1070,7 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mwarn-mcu @gol
|
||||
-mcode-region= -mdata-region= @gol
|
||||
-msilicon-errata= -msilicon-errata-warn= @gol
|
||||
-mhwmult= -minrt -mtiny-printf}
|
||||
-mhwmult= -minrt -mtiny-printf -mmax-inline-shift=}
|
||||
|
||||
@emph{NDS32 Options}
|
||||
@gccoptlist{-mbig-endian -mlittle-endian @gol
|
||||
|
@ -24816,6 +24816,19 @@ buffered before it is sent to write.
|
|||
This option requires Newlib Nano IO, so GCC must be configured with
|
||||
@samp{--enable-newlib-nano-formatted-io}.
|
||||
|
||||
@item -mmax-inline-shift=
|
||||
@opindex mmax-inline-shift=
|
||||
This option takes an integer between 0 and 64 inclusive, and sets
|
||||
the maximum number of inline shift instructions which should be emitted to
|
||||
perform a shift operation by a constant amount. When this value needs to be
|
||||
exceeded, an mspabi helper function is used instead. The default value is 4.
|
||||
|
||||
This only affects cases where a shift by multiple positions cannot be
|
||||
completed with a single instruction (e.g. all shifts >1 on the 430 ISA).
|
||||
|
||||
Shifts of a 32-bit value are at least twice as costly, so the value passed for
|
||||
this option is divided by 2 and the resulting value used instead.
|
||||
|
||||
@item -mcode-region=
|
||||
@itemx -mdata-region=
|
||||
@opindex mcode-region
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" } { "" } } */
|
||||
/* { dg-options "-Os" } */
|
||||
/* { dg-final { scan-assembler-not "mspabi_srli" } } */
|
||||
/* { dg-final { scan-assembler "rrum" } } */
|
||||
/* { dg-final { scan-assembler "RRUM" } } */
|
||||
|
||||
/* Ensure that HImode shifts with source operand in memory are emulated with a
|
||||
rotate instructions. */
|
||||
|
|
|
@ -0,0 +1,52 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430x" "-mlarge" } { "" } } */
|
||||
/* { dg-options "-mcpu=msp430" } */
|
||||
/* { dg-final { scan-assembler-not "__mspabi_slli_4" } } */
|
||||
/* { dg-final { scan-assembler-not "__mspabi_sral_2" } } */
|
||||
/* { dg-final { scan-assembler "__mspabi_slli_5" } } */
|
||||
/* { dg-final { scan-assembler "__mspabi_sral_3" } } */
|
||||
|
||||
/* Test the default value of 4 for -mmax-inline-shift has been observed. */
|
||||
|
||||
volatile int a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15;
|
||||
volatile long l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
|
||||
|
||||
void
|
||||
ashift (void)
|
||||
{
|
||||
a1 <<= 1;
|
||||
a2 <<= 2;
|
||||
a3 <<= 3;
|
||||
a4 <<= 4;
|
||||
a5 <<= 5;
|
||||
a6 <<= 6;
|
||||
a7 <<= 7;
|
||||
a8 <<= 8;
|
||||
a9 <<= 9;
|
||||
a10 <<= 10;
|
||||
a11 <<= 11;
|
||||
a12 <<= 12;
|
||||
a13 <<= 13;
|
||||
a14 <<= 14;
|
||||
a15 <<= 15;
|
||||
}
|
||||
|
||||
void
|
||||
ashiftrt (void)
|
||||
{
|
||||
l1 >>= 1;
|
||||
l2 >>= 2;
|
||||
l3 >>= 3;
|
||||
l4 >>= 4;
|
||||
l5 >>= 5;
|
||||
l6 >>= 6;
|
||||
l7 >>= 7;
|
||||
l8 >>= 8;
|
||||
l9 >>= 9;
|
||||
l10 >>= 10;
|
||||
l11 >>= 11;
|
||||
l12 >>= 12;
|
||||
l13 >>= 13;
|
||||
l14 >>= 14;
|
||||
l15 >>= 15;
|
||||
}
|
|
@ -0,0 +1,50 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430x" "-mlarge" } { "" } } */
|
||||
/* { dg-options "-mcpu=msp430 -mmax-inline-shift=10" } */
|
||||
/* { dg-final { scan-assembler-not "__mspabi_slli_10" } } */
|
||||
/* { dg-final { scan-assembler-not "__mspabi_sral_5" } } */
|
||||
/* { dg-final { scan-assembler "__mspabi_slli_11" } } */
|
||||
/* { dg-final { scan-assembler "__mspabi_sral_6" } } */
|
||||
|
||||
volatile int a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15;
|
||||
volatile long l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
|
||||
|
||||
void
|
||||
ashift (void)
|
||||
{
|
||||
a1 <<= 1;
|
||||
a2 <<= 2;
|
||||
a3 <<= 3;
|
||||
a4 <<= 4;
|
||||
a5 <<= 5;
|
||||
a6 <<= 6;
|
||||
a7 <<= 7;
|
||||
a8 <<= 8;
|
||||
a9 <<= 9;
|
||||
a10 <<= 10;
|
||||
a11 <<= 11;
|
||||
a12 <<= 12;
|
||||
a13 <<= 13;
|
||||
a14 <<= 14;
|
||||
a15 <<= 15;
|
||||
}
|
||||
|
||||
void
|
||||
ashiftrt (void)
|
||||
{
|
||||
l1 >>= 1;
|
||||
l2 >>= 2;
|
||||
l3 >>= 3;
|
||||
l4 >>= 4;
|
||||
l5 >>= 5;
|
||||
l6 >>= 6;
|
||||
l7 >>= 7;
|
||||
l8 >>= 8;
|
||||
l9 >>= 9;
|
||||
l10 >>= 10;
|
||||
l11 >>= 11;
|
||||
l12 >>= 12;
|
||||
l13 >>= 13;
|
||||
l14 >>= 14;
|
||||
l15 >>= 15;
|
||||
}
|
|
@ -0,0 +1,48 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" } { "" } } */
|
||||
/* { dg-options "-mcpu=msp430x -mmax-inline-shift=10" } */
|
||||
/* { dg-final { scan-assembler-not "__mspabi_slli" } } */
|
||||
/* { dg-final { scan-assembler "__mspabi_sral_6" } } */
|
||||
|
||||
volatile int a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15;
|
||||
volatile long l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
|
||||
|
||||
void
|
||||
ashift (void)
|
||||
{
|
||||
a1 <<= 1;
|
||||
a2 <<= 2;
|
||||
a3 <<= 3;
|
||||
a4 <<= 4;
|
||||
a5 <<= 5;
|
||||
a6 <<= 6;
|
||||
a7 <<= 7;
|
||||
a8 <<= 8;
|
||||
a9 <<= 9;
|
||||
a10 <<= 10;
|
||||
a11 <<= 11;
|
||||
a12 <<= 12;
|
||||
a13 <<= 13;
|
||||
a14 <<= 14;
|
||||
a15 <<= 15;
|
||||
}
|
||||
|
||||
void
|
||||
ashiftrt (void)
|
||||
{
|
||||
l1 >>= 1;
|
||||
l2 >>= 2;
|
||||
l3 >>= 3;
|
||||
l4 >>= 4;
|
||||
l5 >>= 5;
|
||||
l6 >>= 6;
|
||||
l7 >>= 7;
|
||||
l8 >>= 8;
|
||||
l9 >>= 9;
|
||||
l10 >>= 10;
|
||||
l11 >>= 11;
|
||||
l12 >>= 12;
|
||||
l13 >>= 13;
|
||||
l14 >>= 14;
|
||||
l15 >>= 15;
|
||||
}
|
|
@ -65,6 +65,21 @@ __mspabi_slli:
|
|||
RET
|
||||
#endif
|
||||
|
||||
#ifdef __MSP430X__
|
||||
.section .text.__gnu_mspabi_sllp
|
||||
1: ADDA #-1,R13
|
||||
ADDA R12,R12
|
||||
.global __gnu_mspabi_sllp
|
||||
__gnu_mspabi_sllp:
|
||||
CMP #0,R13
|
||||
JNZ 1b
|
||||
#ifdef __MSP430X_LARGE__
|
||||
RETA
|
||||
#else
|
||||
RET
|
||||
#endif /* __MSP430X_LARGE__ */
|
||||
#endif /* __MSP430X__ */
|
||||
|
||||
/* Logical Left Shift - R12:R13 -> R12:R13. */
|
||||
|
||||
.section .text.__mspabi_slll_n
|
||||
|
|
|
@ -64,6 +64,21 @@ __mspabi_srai:
|
|||
RET
|
||||
#endif
|
||||
|
||||
#ifdef __MSP430X__
|
||||
.section .text.__gnu_mspabi_srap
|
||||
1: ADDA #-1,R13
|
||||
RRAX.A R12,R12
|
||||
.global __gnu_mspabi_srap
|
||||
__gnu_mspabi_srap:
|
||||
CMP #0,R13
|
||||
JNZ 1b
|
||||
#ifdef __MSP430X_LARGE__
|
||||
RETA
|
||||
#else
|
||||
RET
|
||||
#endif /* __MSP430X_LARGE__ */
|
||||
#endif /* __MSP430X__ */
|
||||
|
||||
/* Arithmetic Right Shift - R12:R13 -> R12:R13. */
|
||||
|
||||
.section .text.__mspabi_sral_n
|
||||
|
|
|
@ -66,6 +66,22 @@ __mspabi_srli:
|
|||
RET
|
||||
#endif
|
||||
|
||||
#ifdef __MSP430X__
|
||||
.section .text.__gnu_mspabi_srlp
|
||||
1: ADDA #-1,R13
|
||||
CLRC
|
||||
RRCX.A R12,R12
|
||||
.global __gnu_mspabi_srlp
|
||||
__gnu_mspabi_srlp:
|
||||
CMP #0,R13
|
||||
JNZ 1b
|
||||
#ifdef __MSP430X_LARGE__
|
||||
RETA
|
||||
#else
|
||||
RET
|
||||
#endif /* __MSP430X_LARGE__ */
|
||||
#endif /* __MSP430X__ */
|
||||
|
||||
/* Logical Right Shift - R12:R13 -> R12:R13. */
|
||||
|
||||
.section .text.__mspabi_srll_n
|
||||
|
|
Loading…
Reference in New Issue