re PR target/85281 (Assembler messages: Error: operand size mismatch for `vpbroadcastb' with -mavx512bw -masm=intel)
PR target/85281
* config/i386/sse.md (reduces<mode><mask_scalar_name>,
avx512f_vmcmp<mode>3<round_saeonly_name>,
avx512f_vmcmp<mode>3_mask<round_saeonly_name>,
avx512f_sgetexp<mode><mask_scalar_name><round_saeonly_scalar_name>,
avx512f_rndscale<mode><round_saeonly_name>,
avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>,
avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
Use %<iptr>2 instead of %2 for -masm=intel.
(avx512f_vcvtss2usi<round_name>, avx512f_vcvtss2usiq<round_name>,
avx512f_vcvttss2usi<round_saeonly_name>,
avx512f_vcvttss2usiq<round_saeonly_name>): Use %k1 instead of %1 for
-masm=intel.
(avx512f_vcvtsd2usi<round_name>, avx512f_vcvtsd2usiq<round_name>,
avx512f_vcvttsd2usi<round_saeonly_name>,
avx512f_vcvttsd2usiq<round_saeonly_name>, ufloatv2siv2df2<mask_name>):
Use %q1 instead of %1 for -masm=intel.
(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>,
avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Use %<iptr>3 instead
of %3 for -masm=intel.
(sse2_shufpd_v2df_mask): Fix a typo, change %{6%} to %{%6%} for
-masm=intel.
(*avx512vl_<code>v2div2qi2_store): Use %w0 instead of %0 for
-masm=intel.
(*avx512vl_<code><mode>v4qi2_store): Use %k0 instead of %0 for
-masm=intel.
(avx512vl_<code><mode>v4qi2_mask_store): Use a single pattern with
%k0 and %1 for -masm=intel rather than two patterns, one with %0 and
%g1.
(*avx512vl_<code><mode>v8qi2_store): Use %q0 instead of %0 for
-masm=intel.
(avx512vl_<code><mode>v8qi2_mask_store): Use a single pattern with
%q0 and %1 for -masm=intel rather than two patterns, one with %0 and
%g1 and one with %0 and %1.
(avx512er_vmrcp28<mode><round_saeonly_name>,
avx512er_vmrsqrt28<mode><round_saeonly_name>): Use %<iptr>1 instead of
%1 for -masm=intel.
(avx5124fmaddps_4fmaddps_mask, avx5124fmaddps_4fmaddss_mask,
avx5124fmaddps_4fnmaddps_mask, avx5124fmaddps_4fnmaddss_mask,
avx5124vnniw_vp4dpwssd_mask, avx5124vnniw_vp4dpwssds_mask): Swap order
of %0 and %{%4%} for -masm=intel.
(avx5124fmaddps_4fmaddps_maskz, avx5124fmaddps_4fmaddss_maskz,
avx5124fmaddps_4fnmaddps_maskz, avx5124fmaddps_4fnmaddss_maskz,
avx5124vnniw_vp4dpwssd_maskz, avx5124vnniw_vp4dpwssds_maskz): Swap
order of %0 and %{%5%}%{z%} for -masm=intel.
From-SVN: r259430
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
ec214f928c
commit
7044c89cfd
@ -1,3 +1,51 @@
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2018-04-17 Jakub Jelinek <jakub@redhat.com>
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PR target/85281
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* config/i386/sse.md (reduces<mode><mask_scalar_name>,
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avx512f_vmcmp<mode>3<round_saeonly_name>,
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avx512f_vmcmp<mode>3_mask<round_saeonly_name>,
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avx512f_sgetexp<mode><mask_scalar_name><round_saeonly_scalar_name>,
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avx512f_rndscale<mode><round_saeonly_name>,
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avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>,
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avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
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Use %<iptr>2 instead of %2 for -masm=intel.
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(avx512f_vcvtss2usi<round_name>, avx512f_vcvtss2usiq<round_name>,
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avx512f_vcvttss2usi<round_saeonly_name>,
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avx512f_vcvttss2usiq<round_saeonly_name>): Use %k1 instead of %1 for
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-masm=intel.
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(avx512f_vcvtsd2usi<round_name>, avx512f_vcvtsd2usiq<round_name>,
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avx512f_vcvttsd2usi<round_saeonly_name>,
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avx512f_vcvttsd2usiq<round_saeonly_name>, ufloatv2siv2df2<mask_name>):
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Use %q1 instead of %1 for -masm=intel.
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(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>,
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avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Use %<iptr>3 instead
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of %3 for -masm=intel.
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(sse2_shufpd_v2df_mask): Fix a typo, change %{6%} to %{%6%} for
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-masm=intel.
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(*avx512vl_<code>v2div2qi2_store): Use %w0 instead of %0 for
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-masm=intel.
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(*avx512vl_<code><mode>v4qi2_store): Use %k0 instead of %0 for
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-masm=intel.
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(avx512vl_<code><mode>v4qi2_mask_store): Use a single pattern with
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%k0 and %1 for -masm=intel rather than two patterns, one with %0 and
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%g1.
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(*avx512vl_<code><mode>v8qi2_store): Use %q0 instead of %0 for
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-masm=intel.
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(avx512vl_<code><mode>v8qi2_mask_store): Use a single pattern with
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%q0 and %1 for -masm=intel rather than two patterns, one with %0 and
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%g1 and one with %0 and %1.
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(avx512er_vmrcp28<mode><round_saeonly_name>,
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avx512er_vmrsqrt28<mode><round_saeonly_name>): Use %<iptr>1 instead of
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%1 for -masm=intel.
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(avx5124fmaddps_4fmaddps_mask, avx5124fmaddps_4fmaddss_mask,
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avx5124fmaddps_4fnmaddps_mask, avx5124fmaddps_4fnmaddss_mask,
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avx5124vnniw_vp4dpwssd_mask, avx5124vnniw_vp4dpwssds_mask): Swap order
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of %0 and %{%4%} for -masm=intel.
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(avx5124fmaddps_4fmaddps_maskz, avx5124fmaddps_4fmaddss_maskz,
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avx5124fmaddps_4fnmaddps_maskz, avx5124fmaddps_4fnmaddss_maskz,
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avx5124vnniw_vp4dpwssd_maskz, avx5124vnniw_vp4dpwssds_maskz): Swap
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order of %0 and %{%5%}%{z%} for -masm=intel.
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2018-04-17 Jan Hubicka <jh@suse.cz>
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PR lto/85405
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@ -2628,7 +2628,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512DQ"
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"vreduce<ssescalarmodesuffix>\t{%3, %2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2, %3}"
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"vreduce<ssescalarmodesuffix>\t{%3, %2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2, %3}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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@ -2796,7 +2796,7 @@
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UNSPEC_PCMP)
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(const_int 1)))]
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"TARGET_AVX512F"
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"vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}"
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"vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %<iptr>2<round_saeonly_op4>, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -2814,7 +2814,7 @@
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(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")
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(const_int 1))))]
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"TARGET_AVX512F"
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"vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_saeonly_op5>, %3}"
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"vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %<iptr>2<round_saeonly_op5>, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -4805,7 +4805,7 @@
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(parallel [(const_int 0)]))]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F"
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"vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
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"vcvtss2usi\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "SI")])
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@ -4818,7 +4818,7 @@
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(parallel [(const_int 0)]))]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F && TARGET_64BIT"
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"vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
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"vcvtss2usi\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "DI")])
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@ -4830,7 +4830,7 @@
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(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(parallel [(const_int 0)]))))]
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"TARGET_AVX512F"
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"vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
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"vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "SI")])
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@ -4842,7 +4842,7 @@
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(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(parallel [(const_int 0)]))))]
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"TARGET_AVX512F && TARGET_64BIT"
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"vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
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"vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "DI")])
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@ -4855,7 +4855,7 @@
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(parallel [(const_int 0)]))]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F"
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"vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
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"vcvtsd2usi\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "SI")])
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@ -4868,7 +4868,7 @@
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(parallel [(const_int 0)]))]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F && TARGET_64BIT"
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"vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
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"vcvtsd2usi\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "DI")])
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@ -4880,7 +4880,7 @@
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(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(parallel [(const_int 0)]))))]
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"TARGET_AVX512F"
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"vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
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"vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "SI")])
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@ -4892,7 +4892,7 @@
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(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(parallel [(const_int 0)]))))]
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"TARGET_AVX512F && TARGET_64BIT"
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"vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
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"vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "DI")])
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@ -5099,7 +5099,7 @@
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(match_operand:V4SI 1 "nonimmediate_operand" "vm")
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(parallel [(const_int 0) (const_int 1)]))))]
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"TARGET_AVX512VL"
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"vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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"vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "V2DF")])
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@ -8504,7 +8504,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512F"
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"vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1, %2<round_saeonly_scalar_mask_op3>}";
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"vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1, %<iptr>2<round_saeonly_scalar_mask_op3>}";
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -8624,7 +8624,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512F"
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %3<round_saeonly_sd_mask_op5>, %4}";
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %<iptr>3<round_saeonly_sd_mask_op5>, %4}";
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -8643,7 +8643,7 @@
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(match_dup 1)
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(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
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"TARGET_AVX512F"
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2, %0%{%5%}|%0%{%5%}, %2, %3<round_saeonly_op6>, %4}";
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2, %0%{%5%}|%0%{%5%}, %2, %<iptr>3<round_saeonly_op6>, %4}";
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -8670,7 +8670,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512F"
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"vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}"
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"vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %<iptr>2<round_saeonly_op4>, %3}"
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[(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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@ -8861,7 +8861,7 @@
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mask |= (INTVAL (operands[4]) - 2) << 1;
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operands[3] = GEN_INT (mask);
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return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{6%}%N5, %1, %2, %3}";
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return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{%6%}%N5, %1, %2, %3}";
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}
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[(set_attr "type" "sseshuf")
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(set_attr "length_immediate" "1")
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@ -9514,7 +9514,7 @@
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_AVX512VL"
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"vpmov<trunsuffix>qb\t{%1, %0|%0, %1}"
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"vpmov<trunsuffix>qb\t{%1, %0|%w0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "memory" "store")
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(set_attr "prefix" "evex")
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@ -9604,7 +9604,7 @@
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_AVX512VL"
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"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}"
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"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%k0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "memory" "store")
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(set_attr "prefix" "evex")
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@ -9674,11 +9674,7 @@
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_AVX512VL"
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{
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if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 8)
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return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}";
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return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
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}
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"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "memory" "store")
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(set_attr "prefix" "evex")
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@ -9699,7 +9695,7 @@
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_AVX512VL"
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"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}"
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"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%q0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "memory" "store")
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(set_attr "prefix" "evex")
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@ -9769,11 +9765,7 @@
|
||||
(const_int 12) (const_int 13)
|
||||
(const_int 14) (const_int 15)]))))]
|
||||
"TARGET_AVX512VL"
|
||||
{
|
||||
if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4)
|
||||
return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
|
||||
return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
|
||||
}
|
||||
"vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%q0%{%2%}, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "memory" "store")
|
||||
(set_attr "prefix" "evex")
|
||||
@ -16426,7 +16418,7 @@
|
||||
(match_operand:VF_128 2 "register_operand" "v")
|
||||
(const_int 1)))]
|
||||
"TARGET_AVX512ER"
|
||||
"vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %1<round_saeonly_op3>}"
|
||||
"vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %<iptr>1<round_saeonly_op3>}"
|
||||
[(set_attr "length_immediate" "1")
|
||||
(set_attr "prefix" "evex")
|
||||
(set_attr "type" "sse")
|
||||
@ -16452,7 +16444,7 @@
|
||||
(match_operand:VF_128 2 "register_operand" "v")
|
||||
(const_int 1)))]
|
||||
"TARGET_AVX512ER"
|
||||
"vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %1<round_saeonly_op3>}"
|
||||
"vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %<iptr>1<round_saeonly_op3>}"
|
||||
[(set_attr "length_immediate" "1")
|
||||
(set_attr "type" "sse")
|
||||
(set_attr "prefix" "evex")
|
||||
@ -19595,7 +19587,7 @@
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_AVX512DQ"
|
||||
"vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2<round_saeonly_scalar_mask_op4>, %3}"
|
||||
"vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "prefix" "evex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
@ -19650,7 +19642,7 @@
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_AVX512F"
|
||||
"vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2<round_saeonly_scalar_mask_op4>, %3}";
|
||||
"vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}";
|
||||
[(set_attr "prefix" "evex")
|
||||
(set_attr "mode" "<ssescalarmode>")])
|
||||
|
||||
@ -19942,7 +19934,7 @@
|
||||
(match_operand:V16SF 3 "register_operand" "0")
|
||||
(match_operand:HI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
|
||||
"v4fmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("V16SF"))])
|
||||
@ -19957,7 +19949,7 @@
|
||||
(match_operand:V16SF 4 "const0_operand" "C")
|
||||
(match_operand:HI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
|
||||
"v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("V16SF"))])
|
||||
@ -19983,7 +19975,7 @@
|
||||
(match_operand:V4SF 3 "register_operand" "0")
|
||||
(match_operand:QI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}"
|
||||
"v4fmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("SF"))])
|
||||
@ -19998,7 +19990,7 @@
|
||||
(match_operand:V4SF 4 "const0_operand" "C")
|
||||
(match_operand:QI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}"
|
||||
"v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("SF"))])
|
||||
@ -20024,7 +20016,7 @@
|
||||
(match_operand:V16SF 3 "register_operand" "0")
|
||||
(match_operand:HI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fnmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
|
||||
"v4fnmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("V16SF"))])
|
||||
@ -20039,7 +20031,7 @@
|
||||
(match_operand:V16SF 4 "const0_operand" "C")
|
||||
(match_operand:HI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
|
||||
"v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("V16SF"))])
|
||||
@ -20065,7 +20057,7 @@
|
||||
(match_operand:V4SF 3 "register_operand" "0")
|
||||
(match_operand:QI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fnmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}"
|
||||
"v4fnmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("SF"))])
|
||||
@ -20080,7 +20072,7 @@
|
||||
(match_operand:V4SF 4 "const0_operand" "C")
|
||||
(match_operand:QI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124FMAPS"
|
||||
"v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}"
|
||||
"v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("SF"))])
|
||||
@ -20106,7 +20098,7 @@
|
||||
(match_operand:V16SI 3 "register_operand" "0")
|
||||
(match_operand:HI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124VNNIW"
|
||||
"vp4dpwssd\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
|
||||
"vp4dpwssd\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("TI"))])
|
||||
@ -20121,7 +20113,7 @@
|
||||
(match_operand:V16SI 4 "const0_operand" "C")
|
||||
(match_operand:HI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124VNNIW"
|
||||
"vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
|
||||
"vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("TI"))])
|
||||
@ -20147,7 +20139,7 @@
|
||||
(match_operand:V16SI 3 "register_operand" "0")
|
||||
(match_operand:HI 4 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124VNNIW"
|
||||
"vp4dpwssds\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
|
||||
"vp4dpwssds\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("TI"))])
|
||||
@ -20162,7 +20154,7 @@
|
||||
(match_operand:V16SI 4 "const0_operand" "C")
|
||||
(match_operand:HI 5 "register_operand" "Yk")))]
|
||||
"TARGET_AVX5124VNNIW"
|
||||
"vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
|
||||
"vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
|
||||
[(set_attr ("type") ("ssemuladd"))
|
||||
(set_attr ("prefix") ("evex"))
|
||||
(set_attr ("mode") ("TI"))])
|
||||
|
||||
Loading…
Reference in New Issue
Block a user