Add IFN_COND_FMIN/FMAX functions
This patch adds conditional forms of FMAX and FMIN, following
the pattern for existing conditional binary functions.
gcc/
* doc/md.texi (cond_fmin@var{mode}, cond_fmax@var{mode}): Document.
* optabs.def (cond_fmin_optab, cond_fmax_optab): New optabs.
* internal-fn.def (COND_FMIN, COND_FMAX): New functions.
* internal-fn.c (first_commutative_argument): Handle them.
(FOR_EACH_COND_FN_PAIR): Likewise.
* match.pd (UNCOND_BINARY, COND_BINARY): Likewise.
* config/aarch64/aarch64-sve.md (cond_<fmaxmin><mode>): New
pattern.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_fmaxnm_5.c: New test.
* gcc.target/aarch64/sve/cond_fmaxnm_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_6.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_6_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_7.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_7_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_8.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_8_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_5.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_6.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_6_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_7.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_7_run.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_8.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_8_run.c: Likewise.
This commit is contained in:
Richard Sandiford
parent
bf5f41e4fc
commit
7061300025
@ -6287,7 +6287,7 @@
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;; -------------------------------------------------------------------------
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;; Unpredicated fmax/fmin (the libm functions). The optabs for the
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;; smin/smax rtx codes are handled in the generic section above.
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;; smax/smin rtx codes are handled in the generic section above.
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(define_expand "<fmaxmin><mode>3"
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[(set (match_operand:SVE_FULL_F 0 "register_operand")
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(unspec:SVE_FULL_F
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@ -6302,6 +6302,23 @@
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}
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)
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;; Predicated fmax/fmin (the libm functions). The optabs for the
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;; smax/smin rtx codes are handled in the generic section above.
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(define_expand "cond_<fmaxmin><mode>"
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[(set (match_operand:SVE_FULL_F 0 "register_operand")
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(unspec:SVE_FULL_F
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[(match_operand:<VPRED> 1 "register_operand")
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(unspec:SVE_FULL_F
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[(match_dup 1)
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(const_int SVE_RELAXED_GP)
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(match_operand:SVE_FULL_F 2 "register_operand")
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(match_operand:SVE_FULL_F 3 "aarch64_sve_float_maxmin_operand")]
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SVE_COND_FP_MAXMIN_PUBLIC)
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(match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero")]
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UNSPEC_SEL))]
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"TARGET_SVE"
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)
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;; Predicated floating-point maximum/minimum.
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(define_insn "@aarch64_pred_<optab><mode>"
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[(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?&w, ?&w")
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@ -6930,6 +6930,8 @@ operand 0, otherwise (operand 2 + operand 3) is moved.
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@cindex @code{cond_smax@var{mode}} instruction pattern
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@cindex @code{cond_umin@var{mode}} instruction pattern
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@cindex @code{cond_umax@var{mode}} instruction pattern
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@cindex @code{cond_fmin@var{mode}} instruction pattern
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@cindex @code{cond_fmax@var{mode}} instruction pattern
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@cindex @code{cond_ashl@var{mode}} instruction pattern
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@cindex @code{cond_ashr@var{mode}} instruction pattern
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@cindex @code{cond_lshr@var{mode}} instruction pattern
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@ -6947,6 +6949,8 @@ operand 0, otherwise (operand 2 + operand 3) is moved.
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@itemx @samp{cond_smax@var{mode}}
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@itemx @samp{cond_umin@var{mode}}
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@itemx @samp{cond_umax@var{mode}}
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@itemx @samp{cond_fmin@var{mode}}
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@itemx @samp{cond_fmax@var{mode}}
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@itemx @samp{cond_ashl@var{mode}}
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@itemx @samp{cond_ashr@var{mode}}
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@itemx @samp{cond_lshr@var{mode}}
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@ -3842,6 +3842,8 @@ first_commutative_argument (internal_fn fn)
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case IFN_COND_MUL:
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case IFN_COND_MIN:
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case IFN_COND_MAX:
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case IFN_COND_FMIN:
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case IFN_COND_FMAX:
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case IFN_COND_AND:
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case IFN_COND_IOR:
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case IFN_COND_XOR:
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@ -3961,6 +3963,8 @@ conditional_internal_fn_code (internal_fn ifn)
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/* Invoke T(IFN) for each internal function IFN that also has an
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IFN_COND_* form. */
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#define FOR_EACH_COND_FN_PAIR(T) \
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T (FMAX) \
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T (FMIN) \
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T (FMA) \
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T (FMS) \
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T (FNMA) \
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@ -188,6 +188,8 @@ DEF_INTERNAL_SIGNED_OPTAB_FN (COND_MIN, ECF_CONST, first,
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cond_smin, cond_umin, cond_binary)
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DEF_INTERNAL_SIGNED_OPTAB_FN (COND_MAX, ECF_CONST, first,
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cond_smax, cond_umax, cond_binary)
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DEF_INTERNAL_OPTAB_FN (COND_FMIN, ECF_CONST, cond_fmin, cond_binary)
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DEF_INTERNAL_OPTAB_FN (COND_FMAX, ECF_CONST, cond_fmax, cond_binary)
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DEF_INTERNAL_OPTAB_FN (COND_AND, ECF_CONST | ECF_NOTHROW,
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cond_and, cond_binary)
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DEF_INTERNAL_OPTAB_FN (COND_IOR, ECF_CONST | ECF_NOTHROW,
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@ -90,12 +90,14 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
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plus minus
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mult trunc_div trunc_mod rdiv
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min max
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IFN_FMIN IFN_FMAX
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bit_and bit_ior bit_xor
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lshift rshift)
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(define_operator_list COND_BINARY
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IFN_COND_ADD IFN_COND_SUB
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IFN_COND_MUL IFN_COND_DIV IFN_COND_MOD IFN_COND_RDIV
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IFN_COND_MIN IFN_COND_MAX
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IFN_COND_FMIN IFN_COND_FMAX
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IFN_COND_AND IFN_COND_IOR IFN_COND_XOR
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IFN_COND_SHL IFN_COND_SHR)
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@ -241,6 +241,8 @@ OPTAB_D (cond_smin_optab, "cond_smin$a")
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OPTAB_D (cond_smax_optab, "cond_smax$a")
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OPTAB_D (cond_umin_optab, "cond_umin$a")
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OPTAB_D (cond_umax_optab, "cond_umax$a")
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OPTAB_D (cond_fmin_optab, "cond_fmin$a")
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OPTAB_D (cond_fmax_optab, "cond_fmax$a")
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OPTAB_D (cond_fma_optab, "cond_fma$a")
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OPTAB_D (cond_fms_optab, "cond_fms$a")
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OPTAB_D (cond_fnma_optab, "cond_fnma$a")
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28
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
Normal file
28
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
Normal file
@ -0,0 +1,28 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_1.c"
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
Normal file
@ -0,0 +1,4 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_1_run.c"
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22
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
Normal file
22
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
Normal file
@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_2.c"
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 3 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
Normal file
@ -0,0 +1,4 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_2_run.c"
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27
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
Normal file
27
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
Normal file
@ -0,0 +1,27 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_3.c"
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
Normal file
@ -0,0 +1,4 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_3_run.c"
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26
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
Normal file
26
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
Normal file
@ -0,0 +1,26 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_fmaxnm_4.c"
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z, z[0-9]+\.d\n} 3 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
|
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
Normal file
@ -0,0 +1,4 @@
|
||||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_fmaxnm_4_run.c"
|
||||
29
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
Normal file
29
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
Normal file
@ -0,0 +1,29 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#define FN(X) __builtin_fmin##X
|
||||
#include "cond_fmaxnm_1.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
|
||||
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
Normal file
@ -0,0 +1,4 @@
|
||||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_fminnm_1_run.c"
|
||||
23
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
Normal file
23
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
Normal file
@ -0,0 +1,23 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#define FN(X) __builtin_fmin##X
|
||||
#include "cond_fmaxnm_2.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
Normal file
@ -0,0 +1,4 @@
|
||||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_fminnm_2_run.c"
|
||||
28
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
Normal file
28
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
Normal file
@ -0,0 +1,28 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#define FN(X) __builtin_fmin##X
|
||||
#include "cond_fmaxnm_3.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
|
||||
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
Normal file
@ -0,0 +1,4 @@
|
||||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_fminnm_3_run.c"
|
||||
27
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
Normal file
27
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
Normal file
@ -0,0 +1,27 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#define FN(X) __builtin_fmin##X
|
||||
#include "cond_fmaxnm_4.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z, z[0-9]+\.d\n} 3 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
Normal file
4
gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
Normal file
@ -0,0 +1,4 @@
|
||||
/* { dg-do run { target aarch64_sve_hw } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_fminnm_4_run.c"
|
||||
Loading…
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Reference in New Issue
Block a user