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Correct the latency of loads in M5100

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gcc/
	* config/mips/m5100.md (m51_int_load): Update the latency to 2.

From-SVN: r236288
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Matthew Fortune 2016-05-16 14:20:47 +00:00 committed by Robert Suchanek
parent b434610704
commit 7065002128
2 changed files with 5 additions and 1 deletions
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gcc/ChangeLog
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@ -1,3 +1,7 @@
2016-05-16 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/m5100.md (m51_int_load): Update the latency to 2.
2016-05-16 Nathan Sidwell <nathan@acm.org>
* config/nvptx/nvptx.c (nvptx_mangle_decl_assembler_name): Revert.

2
gcc/config/mips/m5100.md
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@ -65,7 +65,7 @@
;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
;; prefetch: prefetch, prefetchx
(define_insn_reservation "m51_int_load" 3
(define_insn_reservation "m51_int_load" 2
(and (eq_attr "cpu" "m5100")
(eq_attr "type" "load,prefetch,prefetchx"))
"m51_alu")