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* config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New.

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From-SVN: r101434
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Richard Henderson 2005-06-29 11:22:06 -07:00 committed by Richard Henderson
parent afc1ab6196
commit 70707f6c75
2 changed files with 24 additions and 0 deletions
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gcc/ChangeLog
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@ -1,3 +1,7 @@
2005-06-29 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New.
2005-06-29 Richard Henderson <rth@redhat.com>
* tree-vect-transform.c (vect_min_worthwhile_factor): Declare.

20
gcc/config/alpha/alpha.md
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@ -6361,6 +6361,26 @@
""
"eqv %1,%2,%0"
[(set_attr "type" "ilog")])
(define_expand "vec_shl_<mode>"
[(set (match_operand:VEC 0 "register_operand" "")
(ashift:DI (match_operand:VEC 1 "register_operand" "")
(match_operand:DI 2 "reg_or_6bit_operand" "")))]
""
{
operands[0] = gen_lowpart (DImode, operands[0]);
operands[1] = gen_lowpart (DImode, operands[1]);
})
(define_expand "vec_shr_<mode>"
[(set (match_operand:VEC 0 "register_operand" "")
(lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
(match_operand:DI 2 "reg_or_6bit_operand" "")))]
""
{
operands[0] = gen_lowpart (DImode, operands[0]);
operands[1] = gen_lowpart (DImode, operands[1]);
})
;; Bit field extract patterns which use ext[wlq][lh]