i386: Introduce V2QImode vectorized logic [PR103861]
Add V2QImode logic operations with SSE and GP registers and split them to V4QImode SSE instructions or SImode GP instructions. The patch also fixes PR target/103900. 2022-01-04 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/103861 * config/i386/mmx.md (one_cmplv2qi3): New insn pattern. (one_cmplv2qi3 splitters): New post-reload splitters. (*andnotv2qi3): New insn pattern. (andnotv2qi3 splitters): New post-reload splitters. (<any_logic:code>v2qi3): New insn pattern. (<any_logic:insn>v2qi3 splitters): New post-reload splitters. gcc/testsuite/ChangeLog: PR target/103861 * gcc.target/i386/warn-vect-op-2.c: Adjust warnings. * gcc.target/i386/pr103900.c: New test.
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Uros Bizjak
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dd80200324
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708b87dcb6
@ -2745,6 +2745,45 @@
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"TARGET_SSE2"
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"operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
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(define_insn "one_cmplv2qi2"
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[(set (match_operand:V2QI 0 "register_operand" "=r,&x,&v")
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(not:V2QI
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(match_operand:V2QI 1 "register_operand" "0,x,v")))]
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""
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"#"
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[(set_attr "isa" "*,sse2,avx512vl")
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(set_attr "type" "negnot,sselog,sselog")
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(set_attr "mode" "SI,TI,TI")])
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(define_split
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[(set (match_operand:V2QI 0 "general_reg_operand")
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(not:V2QI
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(match_operand:V2QI 1 "general_reg_operand")))]
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"reload_completed"
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[(set (match_dup 0)
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(not:SI (match_dup 1)))]
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{
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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})
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(define_split
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[(set (match_operand:V2QI 0 "sse_reg_operand")
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(not:V2QI
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(match_operand:V2QI 1 "sse_reg_operand")))]
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"TARGET_SSE2 && reload_completed"
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[(set (match_dup 0)
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(xor:V4QI
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(match_dup 0) (match_dup 1)))]
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{
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emit_insn
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(gen_rtx_SET (gen_rtx_REG (V16QImode, REGNO (operands[0])),
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CONSTM1_RTX (V16QImode)));
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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})
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(define_insn "mmx_andnot<mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
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(and:MMXMODEI
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@ -2775,6 +2814,69 @@
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(set_attr "type" "sselog")
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(set_attr "mode" "TI")])
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(define_insn "*andnotv2qi3"
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[(set (match_operand:V2QI 0 "register_operand" "=&r,r,x,x,v")
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(and:V2QI
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(not:V2QI (match_operand:V2QI 1 "register_operand" "0,r,0,x,v"))
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(match_operand:V2QI 2 "register_operand" "r,r,x,x,v")))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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[(set_attr "isa" "*,bmi,sse2_noavx,avx,avx512vl")
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(set_attr "type" "alu,bitmanip,sselog,sselog,sselog")
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(set_attr "mode" "SI,SI,TI,TI,TI")])
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(define_split
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[(set (match_operand:V2QI 0 "general_reg_operand")
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(and:V2QI
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(not:V2QI (match_operand:V2QI 1 "general_reg_operand"))
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(match_operand:V2QI 2 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI && reload_completed"
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[(parallel
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[(set (match_dup 0)
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(and:SI (not:SI (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = gen_lowpart (SImode, operands[2]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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})
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(define_split
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[(set (match_operand:V2QI 0 "general_reg_operand")
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(and:V2QI
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(not:V2QI (match_operand:V2QI 1 "general_reg_operand"))
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(match_operand:V2QI 2 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_BMI && reload_completed"
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[(set (match_dup 0)
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(not:SI (match_dup 1)))
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(parallel
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[(set (match_dup 0)
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(and:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = gen_lowpart (SImode, operands[2]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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})
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(define_split
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[(set (match_operand:V2QI 0 "sse_reg_operand")
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(and:V2QI
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(not:V2QI (match_operand:V2QI 1 "sse_reg_operand"))
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(match_operand:V2QI 2 "sse_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_SSE2 && reload_completed"
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[(set (match_dup 0)
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(and:V4QI (not:V4QI (match_dup 1)) (match_dup 2)))]
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{
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operands[2] = gen_lowpart (V4QImode, operands[2]);
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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})
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(define_expand "mmx_<code><mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand")
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(any_logic:MMXMODEI
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@ -2821,6 +2923,50 @@
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(set_attr "type" "sselog")
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(set_attr "mode" "TI")])
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(define_insn "<code>v2qi3"
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[(set (match_operand:V2QI 0 "register_operand" "=r,x,x,v")
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(any_logic:V2QI
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(match_operand:V2QI 1 "register_operand" "%0,0,x,v")
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(match_operand:V2QI 2 "register_operand" "r,x,x,v")))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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[(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
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(set_attr "type" "alu,sselog,sselog,sselog")
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(set_attr "mode" "SI,TI,TI,TI")])
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(define_split
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[(set (match_operand:V2QI 0 "general_reg_operand")
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(any_logic:V2QI
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(match_operand:V2QI 1 "general_reg_operand")
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(match_operand:V2QI 2 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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[(parallel
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[(set (match_dup 0)
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(any_logic:SI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = gen_lowpart (SImode, operands[2]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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})
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(define_split
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[(set (match_operand:V2QI 0 "sse_reg_operand")
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(any_logic:V2QI
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(match_operand:V2QI 1 "sse_reg_operand")
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(match_operand:V2QI 2 "sse_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_SSE2 && reload_completed"
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[(set (match_dup 0)
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(any_logic:V4QI (match_dup 1) (match_dup 2)))]
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{
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operands[2] = gen_lowpart (V4QImode, operands[2]);
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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})
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel integral element swizzling
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25
gcc/testsuite/gcc.target/i386/pr103900.c
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25
gcc/testsuite/gcc.target/i386/pr103900.c
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@ -0,0 +1,25 @@
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/* PR target/103900 */
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/* { dg-do compile } */
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/* { dg-options "-O -fno-tree-dce -fno-tree-dse" } */
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typedef unsigned char __attribute__((__vector_size__(2))) T;
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typedef unsigned char __attribute__((__vector_size__(32))) U;
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typedef int __attribute__((__vector_size__(64))) V;
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typedef int __attribute__((__vector_size__(32))) W;
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T foo0_v128u8_0;
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U foo0_v256u8_0;
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T foo0_v16u16_0;
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int foo0_v128u64_0, foo0_v512u64_0;
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void
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foo0() {
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V v512u128_0;
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T v16u8_0;
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foo0_v128u64_0 += (short)v16u8_0;
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T v16u8_1 = ~__builtin_shufflevector(foo0_v128u8_0, foo0_v256u8_0, 0, 5);
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W v256u128_1;
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V v512u8_r =
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foo0_v512u64_0 + v512u128_0;
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(union {U b;}){}.b + (U)v256u128_1;
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T v16u8_r = v16u8_0 + v16u8_1 + foo0_v16u16_0;
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}
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@ -14,7 +14,7 @@ int main (int argc, char *argv[])
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v0 + v1, /* { dg-warning "expanded piecewise" } */
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v0 - v1, /* { dg-warning "expanded piecewise" } */
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v0 > v1, /* { dg-warning "expanded piecewise" } */
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v0 & v1, /* { dg-warning "expanded in parallel" } */
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v0 & v1, /* { dg-warning "expanded piecewise" } */
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__builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */
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__builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */
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};
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