* config/cris/cris.md ("*andhi_lowpart_non_v32", "*andhi_lowpart_v32")
("*andqi_lowpart_non_v32", "*andqi_lowpart_v32"): Use "+" for the operand 0 constraint, not "=". From-SVN: r134236
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@ -1,3 +1,9 @@
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2008-04-13 Hans-Peter Nilsson <hp@axis.com>
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* config/cris/cris.md ("*andhi_lowpart_non_v32", "*andhi_lowpart_v32")
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("*andqi_lowpart_non_v32", "*andqi_lowpart_v32"): Use "+" for the
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operand 0 constraint, not "=".
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2008-04-11 James E. Wilson <wilson@tuliptree.org>
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2008-04-11 James E. Wilson <wilson@tuliptree.org>
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* system.h: Change ASSERT_CHECKING to ENABLE_ASSERT_CHECKING.
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* system.h: Change ASSERT_CHECKING to ENABLE_ASSERT_CHECKING.
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@ -2958,7 +2958,7 @@
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(define_insn "*andhi_lowpart_non_v32"
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(define_insn "*andhi_lowpart_non_v32"
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[(set (strict_low_part
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[(set (strict_low_part
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(match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
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(match_operand:HI 0 "register_operand" "+r,r, r,r,r,r"))
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(and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
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(and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
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(match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
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(match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
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"!TARGET_V32"
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"!TARGET_V32"
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@ -2974,7 +2974,7 @@
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(define_insn "*andhi_lowpart_v32"
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(define_insn "*andhi_lowpart_v32"
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[(set (strict_low_part
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[(set (strict_low_part
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(match_operand:HI 0 "register_operand" "=r,r,r,r,r"))
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(match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
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(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
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(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
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(match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
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(match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
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"TARGET_V32"
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"TARGET_V32"
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@ -3025,7 +3025,7 @@
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(define_insn "*andqi_lowpart_non_v32"
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(define_insn "*andqi_lowpart_non_v32"
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[(set (strict_low_part
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[(set (strict_low_part
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(match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
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(match_operand:QI 0 "register_operand" "+r,r, r,r,r"))
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(and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
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(and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
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(match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
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(match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
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"!TARGET_V32"
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"!TARGET_V32"
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@ -3040,7 +3040,7 @@
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(define_insn "*andqi_lowpart_v32"
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(define_insn "*andqi_lowpart_v32"
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[(set (strict_low_part
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[(set (strict_low_part
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(match_operand:QI 0 "register_operand" "=r,r,r,r"))
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(match_operand:QI 0 "register_operand" "+r,r,r,r"))
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(and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
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(and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
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(match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
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"TARGET_V32"
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"TARGET_V32"
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