[ARM] Optional -mthumb for Thumb only targets
2016-11-18 Terry Guo <terry.guo@arm.com>
Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* common/config/arm/arm-common.c (arm_target_thumb_only): New function.
* config/arm/arm-opts.h: Include arm-flags.h.
(struct arm_arch_core_flag): Define.
(arm_arch_core_flags): Define.
* config/arm/arm-protos.h: Include arm-flags.h
(FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
ARM_FSET_CPU_SUBSET): Move to ...
* config/arm/arm-flags.h: This new file.
* config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
(EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
(TARGET_MODE_SPECS): Define.
(DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.
gcc/testsuite/
* gcc.target/arm/optional_thumb-1.c: New test.
* gcc.target/arm/optional_thumb-2.c: New test.
* gcc.target/arm/optional_thumb-3.c: New test.
From-SVN: r242597
This commit is contained in:
Thomas Preud'homme
parent
05237cf81e
commit
70e73d3c42
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@ -1,3 +1,37 @@
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2016-11-18 Terry Guo <terry.guo@arm.com>
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Thomas Preud'homme <thomas.preudhomme@arm.com>
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* common/config/arm/arm-common.c (arm_target_thumb_only): New function.
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* config/arm/arm-opts.h: Include arm-flags.h.
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(struct arm_arch_core_flag): Define.
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(arm_arch_core_flags): Define.
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* config/arm/arm-protos.h: Include arm-flags.h
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(FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
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FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
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FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
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FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
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FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
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FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
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FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
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FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
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FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
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FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
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FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
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FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
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FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
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FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
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ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
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ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
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ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
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ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
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ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
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ARM_FSET_CPU_SUBSET): Move to ...
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* config/arm/arm-flags.h: This new file.
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* config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
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(EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
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(TARGET_MODE_SPECS): Define.
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(DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.
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2016-11-18 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M,
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@ -98,6 +98,29 @@ arm_rewrite_mcpu (int argc, const char **argv)
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return arm_rewrite_selected_cpu (argv[argc - 1]);
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}
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/* Called by the driver to check whether the target denoted by current
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command line options is a Thumb-only target. ARGV is an array of
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-march and -mcpu values (ie. it contains the rhs after the equal
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sign) and we use the last one of them to make a decision. The
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number of elements in ARGV is given in ARGC. */
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const char *
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arm_target_thumb_only (int argc, const char **argv)
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{
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unsigned int opt;
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if (argc)
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{
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for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++)
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if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0)
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&& !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM))
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return "-mthumb";
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return NULL;
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}
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else
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return NULL;
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}
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#undef ARM_CPU_NAME_LENGTH
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@ -0,0 +1,211 @@
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/* Flags used to identify the presence of processor capabilities.
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Copyright (C) 2016 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_ARM_FLAGS_H
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#define GCC_ARM_FLAGS_H
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/* Flags used to identify the presence of processor capabilities. */
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/* Bit values used to identify processor capabilities. */
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#define FL_NONE (0U) /* No flags. */
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#define FL_ANY (0xffffffffU) /* All flags. */
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#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */
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#define FL_ARCH3M (1U << 1) /* Extended multiply. */
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#define FL_MODE26 (1U << 2) /* 26-bit mode support. */
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#define FL_MODE32 (1U << 3) /* 32-bit mode support. */
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#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
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#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
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#define FL_THUMB (1U << 6) /* Thumb aware. */
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#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
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#define FL_STRONG (1U << 8) /* StrongARM. */
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#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
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#define FL_XSCALE (1U << 10) /* XScale. */
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/* spare (1U << 11) */
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#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
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media instructions. */
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#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
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#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
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Note: ARM6 & 7 derivatives only. */
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#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
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#define FL_THUMB2 (1U << 16) /* Thumb-2. */
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#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
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profile. */
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#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */
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#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */
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#define FL_NEON (1U << 20) /* Neon instructions. */
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#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M
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architecture. */
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#define FL_ARCH7 (1U << 22) /* Architecture 7. */
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#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
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#define FL_ARCH8 (1U << 24) /* Architecture 8. */
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#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
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#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
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#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
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#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
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technology". */
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#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2
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technology". */
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#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */
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#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */
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#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */
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#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and
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later. */
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/* Flags that only effect tuning, not available instructions. */
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#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
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| FL_CO_PROC)
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#define FL_FOR_ARCH2 FL_NOTM
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#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
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#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
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#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
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#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
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#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
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#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
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#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
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#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
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#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
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#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
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#define FL_FOR_ARCH6J FL_FOR_ARCH6
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#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
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#define FL_FOR_ARCH6Z FL_FOR_ARCH6
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#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
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#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
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#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
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#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
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#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
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#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
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#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
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#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
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#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
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#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
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#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
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#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
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#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
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#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
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#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8)
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/* There are too many feature bits to fit in a single word so the set of cpu and
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fpu capabilities is a structure. A feature set is created and manipulated
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with the ARM_FSET macros. */
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typedef struct
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{
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unsigned cpu[2];
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} arm_feature_set;
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/* Initialize a feature set. */
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#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
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#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
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#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
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/* Accessors. */
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#define ARM_FSET_CPU1(S) ((S).cpu[0])
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#define ARM_FSET_CPU2(S) ((S).cpu[1])
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/* Useful combinations. */
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#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
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#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
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/* Tests for a specific CPU feature. */
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#define ARM_FSET_HAS_CPU1(A, F) \
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(((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
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#define ARM_FSET_HAS_CPU2(A, F) \
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(((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
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#define ARM_FSET_HAS_CPU(A, F1, F2) \
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(ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
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/* Add a feature to a feature set. */
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#define ARM_FSET_ADD_CPU1(DST, F) \
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do { \
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(DST).cpu[0] |= (F); \
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} while (0)
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#define ARM_FSET_ADD_CPU2(DST, F) \
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do { \
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(DST).cpu[1] |= (F); \
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} while (0)
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/* Remove a feature from a feature set. */
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#define ARM_FSET_DEL_CPU1(DST, F) \
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do { \
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(DST).cpu[0] &= ~(F); \
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} while (0)
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#define ARM_FSET_DEL_CPU2(DST, F) \
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do { \
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(DST).cpu[1] &= ~(F); \
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} while (0)
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/* Union of feature sets. */
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#define ARM_FSET_UNION(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
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} while (0)
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/* Intersection of feature sets. */
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#define ARM_FSET_INTER(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
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} while (0)
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/* Exclusive disjunction. */
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#define ARM_FSET_XOR(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
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} while (0)
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/* Difference of feature sets: F1 excluding the elements of F2. */
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#define ARM_FSET_EXCLUDE(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
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} while (0)
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/* Test for an empty feature set. */
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#define ARM_FSET_IS_EMPTY(A) \
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(!((A).cpu[0]) && !((A).cpu[1]))
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/* Tests whether the cpu features of A are a subset of B. */
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#define ARM_FSET_CPU_SUBSET(A,B) \
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((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
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&& (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
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#endif /* GCC_ARM_FLAGS_H */
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@ -25,6 +25,8 @@
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#ifndef ARM_OPTS_H
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#define ARM_OPTS_H
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#include "arm-flags.h"
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/* The various ARM cores. */
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enum processor_type
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{
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@ -77,4 +79,24 @@ enum arm_tls_type {
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TLS_GNU,
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TLS_GNU2
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};
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struct arm_arch_core_flag
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{
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const char *const name;
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const arm_feature_set flags;
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};
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static const struct arm_arch_core_flag arm_arch_core_flags[] =
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{
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#undef ARM_CORE
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#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
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{NAME, FLAGS},
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#include "arm-cores.def"
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#undef ARM_CORE
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#undef ARM_ARCH
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#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
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{NAME, FLAGS},
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#include "arm-arches.def"
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#undef ARM_ARCH
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};
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#endif
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@ -22,6 +22,8 @@
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#ifndef GCC_ARM_PROTOS_H
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#define GCC_ARM_PROTOS_H
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#include "arm-flags.h"
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extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
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extern int use_return_insn (int, rtx);
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extern bool use_simple_return_p (void);
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|
|
@ -348,192 +350,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *);
|
|||
|
||||
extern bool arm_is_constant_pool_ref (rtx);
|
||||
|
||||
/* Flags used to identify the presence of processor capabilities. */
|
||||
|
||||
/* Bit values used to identify processor capabilities. */
|
||||
#define FL_NONE (0U) /* No flags. */
|
||||
#define FL_ANY (0xffffffffU) /* All flags. */
|
||||
#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */
|
||||
#define FL_ARCH3M (1U << 1) /* Extended multiply. */
|
||||
#define FL_MODE26 (1U << 2) /* 26-bit mode support. */
|
||||
#define FL_MODE32 (1U << 3) /* 32-bit mode support. */
|
||||
#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
|
||||
#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
|
||||
#define FL_THUMB (1U << 6) /* Thumb aware. */
|
||||
#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
|
||||
#define FL_STRONG (1U << 8) /* StrongARM. */
|
||||
#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
|
||||
#define FL_XSCALE (1U << 10) /* XScale. */
|
||||
/* spare (1U << 11) */
|
||||
#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
|
||||
media instructions. */
|
||||
#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
|
||||
#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
|
||||
Note: ARM6 & 7 derivatives only. */
|
||||
#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
|
||||
#define FL_THUMB2 (1U << 16) /* Thumb-2. */
|
||||
#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
|
||||
profile. */
|
||||
#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */
|
||||
#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */
|
||||
#define FL_NEON (1U << 20) /* Neon instructions. */
|
||||
#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M
|
||||
architecture. */
|
||||
#define FL_ARCH7 (1U << 22) /* Architecture 7. */
|
||||
#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
|
||||
#define FL_ARCH8 (1U << 24) /* Architecture 8. */
|
||||
#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
|
||||
#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
|
||||
#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
|
||||
|
||||
#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
|
||||
technology". */
|
||||
#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2
|
||||
technology". */
|
||||
#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */
|
||||
|
||||
#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */
|
||||
#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */
|
||||
#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and
|
||||
later. */
|
||||
|
||||
/* Flags that only effect tuning, not available instructions. */
|
||||
#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
|
||||
| FL_CO_PROC)
|
||||
|
||||
#define FL_FOR_ARCH2 FL_NOTM
|
||||
#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
|
||||
#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
|
||||
#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
|
||||
#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
|
||||
#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
|
||||
#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
|
||||
#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
|
||||
#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
|
||||
#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
|
||||
#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
|
||||
#define FL_FOR_ARCH6J FL_FOR_ARCH6
|
||||
#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
|
||||
#define FL_FOR_ARCH6Z FL_FOR_ARCH6
|
||||
#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
|
||||
#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
|
||||
#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
|
||||
#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
|
||||
#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
|
||||
#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
|
||||
#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
|
||||
#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
|
||||
#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
|
||||
#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
|
||||
#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
|
||||
#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
|
||||
#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
|
||||
#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
|
||||
#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8)
|
||||
|
||||
/* There are too many feature bits to fit in a single word so the set of cpu and
|
||||
fpu capabilities is a structure. A feature set is created and manipulated
|
||||
with the ARM_FSET macros. */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned cpu[2];
|
||||
} arm_feature_set;
|
||||
|
||||
|
||||
/* Initialize a feature set. */
|
||||
|
||||
#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
|
||||
|
||||
#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
|
||||
#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
|
||||
|
||||
/* Accessors. */
|
||||
|
||||
#define ARM_FSET_CPU1(S) ((S).cpu[0])
|
||||
#define ARM_FSET_CPU2(S) ((S).cpu[1])
|
||||
|
||||
/* Useful combinations. */
|
||||
|
||||
#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
|
||||
#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
|
||||
|
||||
/* Tests for a specific CPU feature. */
|
||||
|
||||
#define ARM_FSET_HAS_CPU1(A, F) \
|
||||
(((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
|
||||
#define ARM_FSET_HAS_CPU2(A, F) \
|
||||
(((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
|
||||
#define ARM_FSET_HAS_CPU(A, F1, F2) \
|
||||
(ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
|
||||
|
||||
/* Add a feature to a feature set. */
|
||||
|
||||
#define ARM_FSET_ADD_CPU1(DST, F) \
|
||||
do { \
|
||||
(DST).cpu[0] |= (F); \
|
||||
} while (0)
|
||||
|
||||
#define ARM_FSET_ADD_CPU2(DST, F) \
|
||||
do { \
|
||||
(DST).cpu[1] |= (F); \
|
||||
} while (0)
|
||||
|
||||
/* Remove a feature from a feature set. */
|
||||
|
||||
#define ARM_FSET_DEL_CPU1(DST, F) \
|
||||
do { \
|
||||
(DST).cpu[0] &= ~(F); \
|
||||
} while (0)
|
||||
|
||||
#define ARM_FSET_DEL_CPU2(DST, F) \
|
||||
do { \
|
||||
(DST).cpu[1] &= ~(F); \
|
||||
} while (0)
|
||||
|
||||
/* Union of feature sets. */
|
||||
|
||||
#define ARM_FSET_UNION(DST,F1,F2) \
|
||||
do { \
|
||||
(DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
|
||||
(DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
|
||||
} while (0)
|
||||
|
||||
/* Intersection of feature sets. */
|
||||
|
||||
#define ARM_FSET_INTER(DST,F1,F2) \
|
||||
do { \
|
||||
(DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
|
||||
(DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
|
||||
} while (0)
|
||||
|
||||
/* Exclusive disjunction. */
|
||||
|
||||
#define ARM_FSET_XOR(DST,F1,F2) \
|
||||
do { \
|
||||
(DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
|
||||
(DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
|
||||
} while (0)
|
||||
|
||||
/* Difference of feature sets: F1 excluding the elements of F2. */
|
||||
|
||||
#define ARM_FSET_EXCLUDE(DST,F1,F2) \
|
||||
do { \
|
||||
(DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
|
||||
(DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
|
||||
} while (0)
|
||||
|
||||
/* Test for an empty feature set. */
|
||||
|
||||
#define ARM_FSET_IS_EMPTY(A) \
|
||||
(!((A).cpu[0]) && !((A).cpu[1]))
|
||||
|
||||
/* Tests whether the cpu features of A are a subset of B. */
|
||||
|
||||
#define ARM_FSET_CPU_SUBSET(A,B) \
|
||||
((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
|
||||
&& (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
|
||||
|
||||
/* The bits in this mask specify which
|
||||
instructions we are allowed to generate. */
|
||||
extern arm_feature_set insn_flags;
|
||||
|
|
|
|||
|
|
@ -2250,13 +2250,18 @@ extern const char *arm_rewrite_mcpu (int argc, const char **argv);
|
|||
" :%{march=*:-march=%*}}" \
|
||||
BIG_LITTLE_SPEC
|
||||
|
||||
extern const char *arm_target_thumb_only (int argc, const char **argv);
|
||||
#define TARGET_MODE_SPEC_FUNCTIONS \
|
||||
{ "target_mode_check", arm_target_thumb_only },
|
||||
|
||||
/* -mcpu=native handling only makes sense with compiler running on
|
||||
an ARM chip. */
|
||||
#if defined(__arm__)
|
||||
extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
# define EXTRA_SPEC_FUNCTIONS \
|
||||
{ "local_cpu_detect", host_detect_local_cpu }, \
|
||||
BIG_LITTLE_CPU_SPEC_FUNCTIONS
|
||||
BIG_LITTLE_CPU_SPEC_FUNCTIONS \
|
||||
TARGET_MODE_SPEC_FUNCTIONS
|
||||
|
||||
# define MCPU_MTUNE_NATIVE_SPECS \
|
||||
" %{march=native:%<march=native %:local_cpu_detect(arch)}" \
|
||||
|
|
@ -2264,10 +2269,21 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
|||
" %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
|
||||
#else
|
||||
# define MCPU_MTUNE_NATIVE_SPECS ""
|
||||
# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
|
||||
# define EXTRA_SPEC_FUNCTIONS \
|
||||
BIG_LITTLE_CPU_SPEC_FUNCTIONS \
|
||||
TARGET_MODE_SPEC_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
|
||||
/* Automatically add -mthumb for Thumb-only targets if mode isn't specified
|
||||
via the configuration option --with-mode or via the command line. The
|
||||
function target_mode_check is called to do the check with either:
|
||||
- an array of -march values if any is given;
|
||||
- an array of -mcpu values if any is given;
|
||||
- an empty array. */
|
||||
#define TARGET_MODE_SPECS \
|
||||
" %{!marm:%{!mthumb:%:target_mode_check(%{march=*:%*;mcpu=*:%*;:})}}"
|
||||
|
||||
#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS
|
||||
#define TARGET_SUPPORTS_WIDE_INT 1
|
||||
|
||||
/* For switching between functions with different target attributes. */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2016-11-18 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* gcc.target/arm/optional_thumb-1.c: New test.
|
||||
* gcc.target/arm/optional_thumb-2.c: New test.
|
||||
* gcc.target/arm/optional_thumb-3.c: New test.
|
||||
|
||||
2016-11-18 Dominik Vogt <vogt@linux.vnet.ibm.com>
|
||||
|
||||
* gcc.target/s390/htm-builtins-1.c (DEFAULT_MAX_REPETITIONS)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
|
||||
/* { dg-options "-march=armv6-m" } */
|
||||
|
||||
/* Check that -mthumb is not needed when compiling for a Thumb-only target. */
|
||||
|
||||
int foo;
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
|
||||
/* { dg-options "-mcpu=cortex-m4" } */
|
||||
|
||||
/* Check that -mthumb is not needed when compiling for a Thumb-only target. */
|
||||
|
||||
int foo;
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target arm_cortex_m } */
|
||||
/* { dg-skip-if "-mthumb given" { *-*-*} { "-mthumb" } } */
|
||||
/* { dg-options "-marm" } */
|
||||
/* { dg-error "target CPU does not support ARM mode" "missing error with -marm on Thumb-only targets" { target *-*-*} 0 } */
|
||||
|
||||
/* Check that -marm gives an error when compiling for a Thumb-only target. */
|
||||
|
||||
int foo;
|
||||
Loading…
Reference in New Issue