ia64.c (ia64_register_move_cost): Add mode arguemnt.
* config/ia64/ia64.c (ia64_register_move_cost): Add mode arguemnt.
Reorganize. Handle ADDL like GR, add GR_AND_BR. Handle TFmode.
(ia64_secondary_reload_class): Need GR between AR/BR and anything.
Need GR between FR and not GR_AND_FR.
* config/ia64/ia64-protos.h (ia64_register_move_cost): Update.
* config/ia64/ia64.h (reg_class): Add GR_AND_BR_REGS, move
AR regs before GR regs.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update.
(PREFERRED_RELOAD_CLASS): Tweak for reordered classes.
(REGISTER_MOVE_COST): Update.
(MEMORY_MOVE_COST): Add GR_AND_FR_REGS.
From-SVN: r45125
This commit is contained in:
Richard Henderson
Richard Henderson
parent
26a952a8a4
commit
7109d28642
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@ -1,3 +1,17 @@
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2001-08-23 Richard Henderson <rth@redhat.com>
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* config/ia64/ia64.c (ia64_register_move_cost): Add mode arguemnt.
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Reorganize. Handle ADDL like GR, add GR_AND_BR. Handle TFmode.
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(ia64_secondary_reload_class): Need GR between AR/BR and anything.
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Need GR between FR and not GR_AND_FR.
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* config/ia64/ia64-protos.h (ia64_register_move_cost): Update.
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* config/ia64/ia64.h (reg_class): Add GR_AND_BR_REGS, move
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AR regs before GR regs.
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(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update.
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(PREFERRED_RELOAD_CLASS): Tweak for reordered classes.
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(REGISTER_MOVE_COST): Update.
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(MEMORY_MOVE_COST): Add GR_AND_FR_REGS.
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2001-08-23 Richard Henderson <rth@redhat.com>
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* regclass.c (init_reg_sets_1): Don't assume cost 2 within
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@ -119,7 +119,8 @@ extern void ia64_asm_output_external PARAMS((FILE *, tree, const char *));
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extern void ia64_encode_section_info PARAMS((tree));
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#endif /* TREE_CODE */
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extern int ia64_register_move_cost PARAMS((enum reg_class, enum reg_class));
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extern int ia64_register_move_cost PARAMS((enum machine_mode, enum reg_class,
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enum reg_class));
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extern int ia64_epilogue_uses PARAMS((int));
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extern void emit_safe_across_calls PARAMS((FILE *));
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extern void ia64_init_builtins PARAMS((void));
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@ -3551,45 +3551,73 @@ ia64_print_operand (file, x, code)
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}
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/* Calulate the cost of moving data from a register in class FROM to
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one in class TO. */
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one in class TO, using MODE. */
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int
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ia64_register_move_cost (from, to)
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ia64_register_move_cost (mode, from, to)
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enum machine_mode mode;
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enum reg_class from, to;
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{
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int from_hard, to_hard;
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int from_gr, to_gr;
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int from_fr, to_fr;
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int from_pr, to_pr;
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/* ADDL_REGS is the same as GR_REGS for movement purposes. */
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if (to == ADDL_REGS)
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to = GR_REGS;
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if (from == ADDL_REGS)
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from = GR_REGS;
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from_hard = (from == BR_REGS || from == AR_M_REGS || from == AR_I_REGS);
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to_hard = (to == BR_REGS || to == AR_M_REGS || to == AR_I_REGS);
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from_gr = (from == GENERAL_REGS);
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to_gr = (to == GENERAL_REGS);
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from_fr = (from == FR_REGS);
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to_fr = (to == FR_REGS);
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from_pr = (from == PR_REGS);
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to_pr = (to == PR_REGS);
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/* All costs are symmetric, so reduce cases by putting the
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lower number class as the destination. */
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if (from < to)
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{
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enum reg_class tmp = to;
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to = from, from = tmp;
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}
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if (from_hard && to_hard)
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return 8;
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else if ((from_hard && !to_gr) || (!from_gr && to_hard))
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return 6;
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/* Moving from FR<->GR in TFmode must be more expensive than 2,
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so that we get secondary memory reloads. Between FR_REGS,
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we have to make this at least as expensive as MEMORY_MOVE_COST
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to avoid spectacularly poor register class preferencing. */
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if (mode == TFmode)
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{
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if (to != GR_REGS || from != GR_REGS)
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return MEMORY_MOVE_COST (mode, to, 0);
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else
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return 3;
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}
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/* Moving between PR registers takes two insns. */
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else if (from_pr && to_pr)
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return 3;
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/* Moving between PR and anything but GR is impossible. */
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else if ((from_pr && !to_gr) || (!from_gr && to_pr))
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return 6;
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switch (to)
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{
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case PR_REGS:
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/* Moving between PR registers takes two insns. */
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if (from == PR_REGS)
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return 3;
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/* Moving between PR and anything but GR is impossible. */
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if (from != GR_REGS)
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return MEMORY_MOVE_COST (mode, to, 0);
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break;
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/* ??? Moving from FR<->GR must be more expensive than 2, so that we get
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secondary memory reloads for TFmode moves. Unfortunately, we don't
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have the mode here, so we can't check that. */
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/* Moreover, we have to make this at least as high as MEMORY_MOVE_COST
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to avoid spectacularly poor register class preferencing for TFmode. */
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else if (from_fr != to_fr)
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return 5;
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case BR_REGS:
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/* Moving between BR and anything but GR is impossible. */
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if (from != GR_REGS && from != GR_AND_BR_REGS)
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return MEMORY_MOVE_COST (mode, to, 0);
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break;
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case AR_I_REGS:
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case AR_M_REGS:
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/* Moving between AR and anything but GR is impossible. */
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if (from != GR_REGS)
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return MEMORY_MOVE_COST (mode, to, 0);
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break;
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case GR_REGS:
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case FR_REGS:
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case GR_AND_FR_REGS:
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case GR_AND_BR_REGS:
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case ALL_REGS:
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break;
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default:
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abort ();
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}
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return 2;
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}
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@ -3613,17 +3641,21 @@ ia64_secondary_reload_class (class, mode, x)
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switch (class)
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{
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case BR_REGS:
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/* ??? This is required because of a bad gcse/cse/global interaction.
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We end up with two pseudos with overlapping lifetimes both of which
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are equiv to the same constant, and both which need to be in BR_REGS.
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This results in a BR_REGS to BR_REGS copy which doesn't exist. To
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reproduce, return NO_REGS here, and compile divdi3 in libgcc2.c.
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This seems to be a cse bug. cse_basic_block_end changes depending
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on the path length, which means the qty_first_reg check in
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make_regs_eqv can give different answers at different times. */
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/* ??? At some point I'll probably need a reload_indi pattern to handle
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this. */
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if (BR_REGNO_P (regno))
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case AR_M_REGS:
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case AR_I_REGS:
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/* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
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interaction. We end up with two pseudos with overlapping lifetimes
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both of which are equiv to the same constant, and both which need
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to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
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changes depending on the path length, which means the qty_first_reg
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check in make_regs_eqv can give different answers at different times.
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At some point I'll probably need a reload_indi pattern to handle
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this.
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We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
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wound up with a FP register from GR_AND_FR_REGS. Extend that to all
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non-general registers for good measure. */
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if (regno >= 0 && ! GENERAL_REGNO_P (regno))
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return GR_REGS;
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/* This is needed if a pseudo used as a call_operand gets spilled to a
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@ -3633,6 +3665,10 @@ ia64_secondary_reload_class (class, mode, x)
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break;
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case FR_REGS:
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/* Need to go through general regsters to get to other class regs. */
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if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
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return GR_REGS;
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/* This can happen when a paradoxical subreg is an operand to the
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muldi3 pattern. */
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/* ??? This shouldn't be necessary after instruction scheduling is
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@ -907,12 +907,13 @@ enum reg_class
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NO_REGS,
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PR_REGS,
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BR_REGS,
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AR_M_REGS,
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AR_I_REGS,
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ADDL_REGS,
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GR_REGS,
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FR_REGS,
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GR_AND_BR_REGS,
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GR_AND_FR_REGS,
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AR_M_REGS,
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AR_I_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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};
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@ -925,8 +926,9 @@ enum reg_class
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/* An initializer containing the names of the register classes as C string
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constants. These names are used in writing some of the debugging dumps. */
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_REGS", \
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"GR_AND_FR_REGS", "AR_M_REGS", "AR_I_REGS", "ALL_REGS" }
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{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
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"ADDL_REGS", "GR_REGS", "FR_REGS", \
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"GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
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/* An initializer containing the contents of the register classes, as integers
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which are bit masks. The Nth integer specifies the contents of class N.
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@ -946,6 +948,14 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00FF }, \
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/* AR_M_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x0C00 }, \
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/* AR_I_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x7000 }, \
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/* ADDL_REGS. */ \
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{ 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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@ -958,18 +968,14 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x0000 }, \
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/* GR_AND_BR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x03FF }, \
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/* GR_AND_FR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x0300 }, \
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/* AR_M_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x0C00 }, \
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/* AR_I_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x7000 }, \
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/* ALL_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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@ -1044,7 +1050,8 @@ enum reg_class
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#define PREFERRED_RELOAD_CLASS(X, CLASS) \
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(CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
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: CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
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: GET_RTX_CLASS (GET_CODE (X)) != 'o' && CLASS > GR_AND_FR_REGS ? NO_REGS \
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: GET_RTX_CLASS (GET_CODE (X)) != 'o' \
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&& (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
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: CLASS)
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/* You should define this macro to indicate to the reload phase that it may
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@ -1882,15 +1889,15 @@ do { \
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#define ADDRESS_COST(ADDRESS) 0
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/* A C expression for the cost of moving data from a register in class FROM to
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one in class TO. */
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one in class TO, using MODE. */
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#define REGISTER_MOVE_COST(MODE, FROM, TO) \
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ia64_register_move_cost((FROM), (TO))
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#define REGISTER_MOVE_COST ia64_register_move_cost
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/* A C expression for the cost of moving data of mode M between a
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register and memory. */
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#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
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((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS ? 4 : 10)
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((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
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|| (CLASS) == GR_AND_FR_REGS ? 4 : 10)
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/* A C expression for the cost of a branch instruction. A value of 1 is the
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default; other values are interpreted relative to that. Used by the
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