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[ARC] Fix unwanted match for sign extend 16-bit constant. 

The combine pass may conclude umulhisi3_imm pattern can accept also sign
extended 16-bit constants. This patch prohibits the combine in considering
this pattern as suitable.

gcc/
2016-04-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
	* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
	(umulhisi3_imm): Update predicates and constraint letters.
	(umulhisi3_reg): Declare instruction as commutative.
	* config/arc/constraints.md (J12, J16): New constraints.
	* config/arc/predicates.md (short_unsigned_const_operand): New
	predicate.
	(arc_short_operand): Likewise.
	* testsuite/gcc.target/arc/umulsihi3_z.c: New file.

From-SVN: r235623
This commit is contained in:
Claudiu Zissulescu 2016-04-29 10:39:22 +02:00 committed by Claudiu Zissulescu
parent 98998245d9
commit 7132ae191b
6 changed files with 62 additions and 5 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2016-04-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
(umulhisi3_imm): Update predicates and constraint letters.
(umulhisi3_reg): Declare instruction as commutative.
* config/arc/constraints.md (J12, J16): New constraints.
* config/arc/predicates.md (short_unsigned_const_operand): New
predicate.
(arc_short_operand): Likewise.
* testsuite/gcc.target/arc/umulsihi3_z.c: New file.
2016-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/13962

2
gcc/config/arc/arc.h
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@ -815,6 +815,8 @@ extern enum reg_class arc_regno_reg_class[];
#define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40)
#define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80)
#define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100)
#define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800)
#define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000)
#define IS_ONE(X) ((X) == 1)
#define IS_ZERO(X) ((X) == 0)

10
gcc/config/arc/arc.md
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@ -1820,7 +1820,7 @@
(define_expand "umulhisi3"
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
(zero_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
(zero_extend:SI (match_operand:HI 2 "arc_short_operand" ""))))]
"TARGET_MPYW"
"{
if (CONSTANT_P (operands[2]))
@ -1832,9 +1832,9 @@
)
(define_insn "umulhisi3_imm"
[(set (match_operand:SI 0 "register_operand" "=r, r,r, r, r")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " 0, r,0, 0, r"))
(match_operand:HI 2 "short_const_int_operand" " L, L,I,C16,C16")))]
[(set (match_operand:SI 0 "register_operand" "=r, r, r, r, r")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, r, 0, 0, r"))
(match_operand:HI 2 "short_unsigned_const_operand" " L, L,J12,J16,J16")))]
"TARGET_MPYW"
"mpyuw%? %0,%1,%2"
[(set_attr "length" "4,4,4,8,8")
@ -1846,7 +1846,7 @@
(define_insn "umulhisi3_reg"
[(set (match_operand:SI 0 "register_operand" "=Rcqq, r, r")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " 0, 0, r"))
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " %0, 0, r"))
(zero_extend:SI (match_operand:HI 2 "register_operand" " Rcqq, r, r"))))]
"TARGET_MPYW"
"mpyuw%? %0,%1,%2"

12
gcc/config/arc/constraints.md
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@ -499,3 +499,15 @@
(define_memory_constraint "ATO"
"A memory with only a base register"
(match_operand 0 "mem_noofs_operand"))
(define_constraint "J12"
"@internal
An unsigned 12-bit integer constant."
(and (match_code "const_int")
(match_test "UNSIGNED_INT12 (ival)")))
(define_constraint "J16"
"@internal
An unsigned 16-bit integer constant"
(and (match_code "const_int")
(match_test "UNSIGNED_INT16 (ival)")))

8
gcc/config/arc/predicates.md
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@ -838,3 +838,11 @@
(ior (match_operand:SI 0 "cmem_address_0")
(match_operand:SI 0 "cmem_address_1")
(match_operand:SI 0 "cmem_address_2")))
(define_predicate "short_unsigned_const_operand"
(and (match_code "const_int")
(match_test "satisfies_constraint_J16 (op)")))
(define_predicate "arc_short_operand"
(ior (match_test "register_operand (op, mode)")
(match_test "short_unsigned_const_operand (op, mode)")))

23
gcc/testsuite/gcc.target/arc/umulsihi3_z.c Normal file
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@ -0,0 +1,23 @@
/* Check if the optimizers are not removing the umulsihi3_imm
instruction. */
/* { dg-do run } */
/* { dg-options "-O2 -fno-inline" } */
#include <stdint.h>
static int32_t test (int16_t reg_val)
{
int32_t x = (reg_val & 0xf) * 62500;
return x;
}
int main (void)
{
volatile int32_t x = 0xc172;
x = test (x);
if (x != 0x0001e848)
__builtin_abort ();
return 0;
}