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predicates.md (ca_operand): Allow subregs. 

2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/predicates.md (ca_operand): Allow subregs.
	(input_operand): Do not allow ca_operand.
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): For the
	carry bit, allow SImode and Pmode.
	(rs6000_init_hard_regno_mode_ok): Make the carry bit class NO_REGS.

From-SVN: r215429
This commit is contained in:
Segher Boessenkool 2014-09-21 19:56:25 +02:00 committed by Segher Boessenkool
parent 1c173a32b1
commit 7143556459
3 changed files with 24 additions and 4 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (ca_operand): Allow subregs.
(input_operand): Do not allow ca_operand.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): For the
carry bit, allow SImode and Pmode.
(rs6000_init_hard_regno_mode_ok): Make the carry bit class NO_REGS.
2014-09-21 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_expand_call): Generate MS->SYSV extra

16
gcc/config/rs6000/predicates.md
View File

@ -116,8 +116,16 @@
;; Return 1 if op is the carry register.
(define_predicate "ca_operand"
(and (match_code "reg")
(match_test "CA_REGNO_P (REGNO (op))")))
(match_operand 0 "register_operand")
{
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
return CA_REGNO_P (REGNO (op));
})
;; Return 1 if op is a signed 5-bit constant integer.
(define_predicate "s5bit_cint_operand"
@ -1121,6 +1129,10 @@
|| GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return register_operand (op, mode);
/* We don't allow moving the carry bit around. */
if (ca_operand (op, mode))
return 0;
/* The only cases left are integral modes one word or smaller (we
do not get called for MODE_CC values). These can be in any
register. */

4
gcc/config/rs6000/rs6000.c
View File

@ -1780,7 +1780,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
return GET_MODE_CLASS (mode) == MODE_CC;
if (CA_REGNO_P (regno))
return mode == BImode;
return mode == Pmode || mode == SImode;
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
@ -2475,7 +2475,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = CA_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;