aarch64: Use RTL builtins for [su]mlal_high intrinsics
Rewrite [su]mlal_high Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-27 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add RTL builtin generator macros. * config/aarch64/aarch64-simd.md (*aarch64_<su>mlal_hi<mode>): Rename to... (aarch64_<su>mlal_hi<mode>_insn): This. (aarch64_<su>mlal_hi<mode>): Define. * config/aarch64/arm_neon.h (vmlal_high_s8): Use RTL builtin instead of inline asm. (vmlal_high_s16): Likewise. (vmlal_high_s32): Likewise. (vmlal_high_u8): Likewise. (vmlal_high_u16): Likewise. (vmlal_high_u32): Likewise.
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@ -240,6 +240,10 @@
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BUILTIN_VQW (TERNOP, smlsl_hi, 0, NONE)
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BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE)
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/* Implemented by aarch64_<su>mlal_hi<mode>. */
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BUILTIN_VQW (TERNOP, smlal_hi, 0, NONE)
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BUILTIN_VQW (TERNOPU, umlal_hi, 0, NONE)
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BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE)
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/* Implemented by aarch64_sqxtun2<mode>. */
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@ -1976,7 +1976,7 @@
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[(set_attr "type" "neon_mla_<Vetype>_long")]
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)
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(define_insn "*aarch64_<su>mlal_hi<mode>"
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(define_insn "aarch64_<su>mlal_hi<mode>_insn"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(plus:<VWIDE>
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(mult:<VWIDE>
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@ -1992,6 +1992,20 @@
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[(set_attr "type" "neon_mla_<Vetype>_long")]
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)
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(define_expand "aarch64_<su>mlal_hi<mode>"
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[(match_operand:<VWIDE> 0 "register_operand")
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(match_operand:<VWIDE> 1 "register_operand")
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(ANY_EXTEND:<VWIDE>(match_operand:VQW 2 "register_operand"))
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(match_operand:VQW 3 "register_operand")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_<su>mlal_hi<mode>_insn (operands[0], operands[1],
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operands[2], p, operands[3]));
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DONE;
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}
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)
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(define_insn "*aarch64_<su>mlsl_lo<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(minus:<VWIDE>
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@ -7316,72 +7316,42 @@ __extension__ extern __inline int16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c)
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{
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int16x8_t __result;
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__asm__ ("smlal2 %0.8h,%2.16b,%3.16b"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_smlal_hiv16qi (__a, __b, __c);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
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{
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int32x4_t __result;
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__asm__ ("smlal2 %0.4s,%2.8h,%3.8h"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_smlal_hiv8hi (__a, __b, __c);
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}
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__extension__ extern __inline int64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
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{
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int64x2_t __result;
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__asm__ ("smlal2 %0.2d,%2.4s,%3.4s"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_smlal_hiv4si (__a, __b, __c);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c)
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{
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uint16x8_t __result;
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__asm__ ("umlal2 %0.8h,%2.16b,%3.16b"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_umlal_hiv16qi_uuuu (__a, __b, __c);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c)
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{
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uint32x4_t __result;
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__asm__ ("umlal2 %0.4s,%2.8h,%3.8h"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_umlal_hiv8hi_uuuu (__a, __b, __c);
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}
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__extension__ extern __inline uint64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlal_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c)
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{
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uint64x2_t __result;
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__asm__ ("umlal2 %0.2d,%2.4s,%3.4s"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_umlal_hiv4si_uuuu (__a, __b, __c);
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}
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__extension__ extern __inline int32x4_t
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