alpha.md (*sadd<modesuffix>): Use ASHIFT instead of MULT rtx.
* config/alpha/alpha.md (*sadd<modesuffix>): Use ASHIFT instead of MULT rtx. Update all corresponding splitters. (*saddl_se): Ditto. (*ssub<modesuffix>): Ditto. (*ssubl_se): Ditto. (*cmp_sadd_di): Update split patterns. (*cmp_sadd_si): Ditto. (*cmp_sadd_sidi): Ditto. (*cmp_ssub_di): Ditto. (*cmp_ssub_si): Ditto. (*cmp_ssub_sidi): Ditto. * config/alpha/predicates.md (const23_operand): New predicate. * config/alpha/alpha.c (alpha_rtx_costs) [PLUS, MINUS]: Look for ASHIFT, not MULT inner operand. (alpha_split_conditional_move): Update for *sadd<modesuffix> change. testsuite/ChangeLog: * gcc.target/alpha/pr83628-1.c: New test. * gcc.target/alpha/pr83628-2.c: Ditto. From-SVN: r256324
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
7f40e113d0
commit
71cacd0b5c
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@ -1,3 +1,22 @@
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2018-01-04 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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* config/alpha/alpha.md (*sadd<modesuffix>): Use ASHIFT
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instead of MULT rtx. Update all corresponding splitters.
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(*saddl_se): Ditto.
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(*ssub<modesuffix>): Ditto.
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(*ssubl_se): Ditto.
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(*cmp_sadd_di): Update split patterns.
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(*cmp_sadd_si): Ditto.
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(*cmp_sadd_sidi): Ditto.
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(*cmp_ssub_di): Ditto.
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(*cmp_ssub_si): Ditto.
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(*cmp_ssub_sidi): Ditto.
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* config/alpha/predicates.md (const23_operand): New predicate.
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* config/alpha/alpha.c (alpha_rtx_costs) [PLUS, MINUS]:
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Look for ASHIFT, not MULT inner operand.
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(alpha_split_conditional_move): Update for *sadd<modesuffix> change.
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2018-01-02 Andrew Waterman <andrew@sifive.com>
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* config/riscv/linux.h (ICACHE_FLUSH_FUNC): New.
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@ -1430,8 +1430,8 @@ alpha_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
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case MINUS:
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if (float_mode_p)
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*total = cost_data->fp_add;
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else if (GET_CODE (XEXP (x, 0)) == MULT
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&& const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
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else if (GET_CODE (XEXP (x, 0)) == ASHIFT
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&& const23_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
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{
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*total = (rtx_cost (XEXP (XEXP (x, 0), 0), mode,
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(enum rtx_code) outer_code, opno, speed)
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@ -2929,8 +2929,8 @@ alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
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add_op = GEN_INT (f);
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if (sext_add_operand (add_op, mode))
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{
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tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
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GEN_INT (diff));
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tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
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GEN_INT (exact_log2 (diff)));
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tmp = gen_rtx_PLUS (DImode, tmp, add_op);
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emit_insn (gen_rtx_SET (target, tmp));
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}
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@ -337,8 +337,8 @@
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"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
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&& INTVAL (operands[2]) % 4 == 0"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
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(match_dup 5))
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(set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3)
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(match_dup 5))
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(match_dup 1))))]
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{
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HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
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@ -348,7 +348,7 @@
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val /= 2, mult = 8;
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operands[4] = GEN_INT (val);
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operands[5] = GEN_INT (mult);
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operands[5] = GEN_INT (exact_log2 (mult));
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})
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(define_split
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@ -519,38 +519,38 @@
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(define_insn "*sadd<modesuffix>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
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(plus:I48MODE
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(mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
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(match_operand:I48MODE 2 "const48_operand" "I,I"))
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(ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
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(match_operand:I48MODE 2 "const23_operand" "I,I"))
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(match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
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""
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"@
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s%2add<modesuffix> %1,%3,%0
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s%2sub<modesuffix> %1,%n3,%0")
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s%P2add<modesuffix> %1,%3,%0
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s%P2sub<modesuffix> %1,%n3,%0")
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(define_insn "*saddl_se"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(sign_extend:DI
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(plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
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(match_operand:SI 2 "const48_operand" "I,I"))
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(plus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
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(match_operand:SI 2 "const23_operand" "I,I"))
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(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
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""
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"@
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s%2addl %1,%3,%0
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s%2subl %1,%n3,%0")
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s%P2addl %1,%3,%0
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s%P2subl %1,%n3,%0")
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(sign_extend:DI
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(plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
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(plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator"
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[(match_operand 2)
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(match_operand 3)])
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(match_operand:SI 4 "const48_operand"))
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(match_operand:SI 4 "const23_operand"))
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(match_operand:SI 5 "sext_add_operand"))))
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(clobber (match_operand:DI 6 "reg_not_elim_operand"))]
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""
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[(set (match_dup 6) (match_dup 7))
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(set (match_dup 0)
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(sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
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(sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4))
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(match_dup 5))))]
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{
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operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
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@ -621,20 +621,20 @@
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(define_insn "*ssub<modesuffix>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(minus:I48MODE
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(mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
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(match_operand:I48MODE 2 "const48_operand" "I"))
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(ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
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(match_operand:I48MODE 2 "const23_operand" "I"))
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(match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
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""
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"s%2sub<modesuffix> %1,%3,%0")
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"s%P2sub<modesuffix> %1,%3,%0")
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(define_insn "*ssubl_se"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
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(match_operand:SI 2 "const48_operand" "I"))
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(minus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
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(match_operand:SI 2 "const23_operand" "I"))
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(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
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""
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"s%2subl %1,%3,%0")
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"s%P2subl %1,%3,%0")
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(define_insn "subv<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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@ -3139,9 +3139,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(plus:DI (mult:DI (match_dup 5) (match_dup 3))
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(plus:DI (ashift:DI (match_dup 5) (match_dup 3))
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(match_dup 4)))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -3164,9 +3165,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(plus:SI (mult:SI (match_dup 6) (match_dup 3))
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(plus:SI (ashift:SI (match_dup 6) (match_dup 3))
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(match_dup 4)))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -3192,9 +3194,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3))
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(sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
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(match_dup 4))))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -3219,9 +3222,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(minus:DI (mult:DI (match_dup 5) (match_dup 3))
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(minus:DI (ashift:DI (match_dup 5) (match_dup 3))
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(match_dup 4)))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -3244,9 +3248,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(minus:SI (mult:SI (match_dup 6) (match_dup 3))
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(minus:SI (ashift:SI (match_dup 6) (match_dup 3))
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(match_dup 4)))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -3272,9 +3277,10 @@
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[(set (match_dup 5)
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(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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(sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3))
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(sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
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(match_dup 4))))]
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (DImode);
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else if (reg_overlap_mentioned_p (operands[5], operands[4]))
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@ -74,6 +74,11 @@
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(and (match_code "const_int,const_wide_int,const_double,const_vector")
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(not (match_test "op == CONST0_RTX (mode)"))))
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;; Return 1 if OP is the constant 2 or 3.
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(define_predicate "const23_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) == 2 || INTVAL (op) == 3")))
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;; Return 1 if OP is the constant 4 or 8.
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(define_predicate "const48_operand"
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(and (match_code "const_int")
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@ -1,3 +1,9 @@
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2018-01-04 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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* gcc.target/alpha/pr83628-1.c: New test.
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* gcc.target/alpha/pr83628-2.c: Ditto.
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2018-01-02 Jakub Jelinek <jakub@redhat.com>
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PR c++/83556
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@ -0,0 +1,19 @@
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/* PR target/83628 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef __SIZE_TYPE__ size_t;
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int
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get_int (int *p, size_t idx)
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{
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return p[idx];
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}
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long
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get_long (long *p, size_t idx)
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{
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return p[idx];
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}
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/* { dg-final { scan-assembler-not "\[ \t\]add\[ql\]" } } */
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@ -0,0 +1,29 @@
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/* PR target/83628 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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int
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s4l (int a, int b)
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{
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return a + b * 4;
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}
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int
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s8l (int a, int b)
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{
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return a + b * 8;
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}
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long
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s4q (long a, long b)
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{
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return a + b * 4;
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}
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long
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s8q (long a, long b)
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{
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return a + b * 8;
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}
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/* { dg-final { scan-assembler-not "\[ \t\]add\[ql\]" } } */
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