[NDS32] Reserve more register numbers for new registers in the future.
gcc/ * config/nds32/nds32.h (FIRST_PSEUDO_REGISTER): Modify. (FIXED_REGISTERS): Reserve more register numbers. (CALL_USED_REGISTERS): Likewise. (REG_ALLOC_ORDER): Likewise. (REG_CLASS_CONTENTS): Likewise. (REGISTER_NAMES): Likewise. Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r254854
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Chung-Ju Wu
Chung-Ju Wu
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@ -1,3 +1,13 @@
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2017-11-17 Chung-Ju Wu <jasonwucj@gmail.com>
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Monk Chiang <sh.chiang04@gmail.com>
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* config/nds32/nds32.h (FIRST_PSEUDO_REGISTER): Modify.
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(FIXED_REGISTERS): Reserve more register numbers.
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(CALL_USED_REGISTERS): Likewise.
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(REG_ALLOC_ORDER): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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(REGISTER_NAMES): Likewise.
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2017-11-17 Chung-Ju Wu <jasonwucj@gmail.com>
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Kito Cheng <kito.cheng@gmail.com>
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@ -530,7 +530,7 @@ enum nds32_builtins
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from 0 to just below FIRST_PSEUDO_REGISTER.
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers. */
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#define FIRST_PSEUDO_REGISTER 34
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#define FIRST_PSEUDO_REGISTER 101
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/* An initializer that says which registers are used for fixed
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purposes all throughout the compiled code and are therefore
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@ -546,19 +546,33 @@ enum nds32_builtins
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reserved for assembler : $r15
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reserved for other use : $r24, $r25, $r26, $r27 */
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#define FIXED_REGISTERS \
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{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
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0, 0, 0, 0, 0, 0, 0, 1, \
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/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
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1, 1, 1, 1, 0, 1, 0, 1, \
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/* ARG_POINTER:32 */ \
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1, \
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/* FRAME_POINTER:33 */ \
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1 \
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#define FIXED_REGISTERS \
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{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
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0, 0, 0, 0, 0, 0, 0, 1, \
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/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
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1, 1, 1, 1, 0, 1, 0, 1, \
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/* AP FP Reserved.................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1 \
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}
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/* Identifies the registers that are not available for
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@ -567,33 +581,53 @@ enum nds32_builtins
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0 : callee-save registers
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1 : caller-save registers */
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#define CALL_USED_REGISTERS \
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{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
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1, 1, 1, 1, 1, 1, 0, 0, \
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/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
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0, 0, 0, 0, 0, 0, 0, 1, \
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/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
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1, 1, 1, 1, 0, 1, 0, 1, \
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/* ARG_POINTER:32 */ \
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1, \
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/* FRAME_POINTER:33 */ \
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1 \
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#define CALL_USED_REGISTERS \
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{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
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1, 1, 1, 1, 1, 1, 0, 0, \
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/* r8 r9 r10 r11 r12 r13 r14 r15 */ \
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0, 0, 0, 0, 0, 0, 0, 1, \
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/* r16 r17 r18 r19 r20 r21 r22 r23 */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* r24 r25 r26 r27 r28 r29 r30 r31 */ \
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1, 1, 1, 1, 0, 1, 0, 1, \
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/* AP FP Reserved.................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1, 1, 1, 1, \
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/* Reserved............................... */ \
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1, 1, 1, 1, 1 \
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}
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/* In nds32 target, we have three levels of registers:
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LOW_COST_REGS : $r0 ~ $r7
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MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
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HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
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#define REG_ALLOC_ORDER \
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{ \
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0, 1, 2, 3, 4, 5, 6, 7, \
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8, 9, 10, 11, 16, 17, 18, 19, \
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12, 13, 14, 15, 20, 21, 22, 23, \
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24, 25, 26, 27, 28, 29, 30, 31, \
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32, \
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33 \
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#define REG_ALLOC_ORDER \
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{ 0, 1, 2, 3, 4, 5, 6, 7, \
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16, 17, 18, 19, 9, 10, 11, 12, \
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13, 14, 8, 15, 20, 21, 22, 23, \
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24, 25, 26, 27, 28, 29, 30, 31, \
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32, 33, 34, 35, 36, 37, 38, 39, \
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40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, \
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64, 65, 66, 67, 68, 69, 70, 71, \
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72, 73, 74, 75, 76, 77, 78, 79, \
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80, 81, 82, 83, 84, 85, 86, 87, \
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88, 89, 90, 91, 92, 93, 94, 95, \
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96, 97, 98, 99, 100, \
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}
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/* Tell IRA to use the order we define rather than messing it up with its
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@ -646,19 +680,30 @@ enum reg_class
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}
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#define REG_CLASS_CONTENTS \
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{ \
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{0x00000000, 0x00000000}, /* NO_REGS */ \
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{0x00000020, 0x00000000}, /* R5_REG : 5 */ \
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{0x00000100, 0x00000000}, /* R8_REG : 8 */ \
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{0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
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{0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
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{0x10000000, 0x00000000}, /* FRAME_POINTER_REG : 28 */ \
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{0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
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{0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
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{0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
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{0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
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{0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
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{0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
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{ /* NO_REGS */ \
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{0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
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/* R5_REG : 5 */ \
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{0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
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/* R8_REG : 8 */ \
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{0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
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/* R15_TA_REG : 15 */ \
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{0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
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/* STACK_REG : 31 */ \
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{0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
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/* FRAME_POINTER_REG : 28 */ \
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{0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
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/* LOW_REGS : 0-7 */ \
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{0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
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/* MIDDLE_REGS : 0-11, 16-19 */ \
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{0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
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/* HIGH_REGS : 12-14, 20-31 */ \
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{0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
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/* GENERAL_REGS : 0-31 */ \
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{0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
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/* FRAME_REGS : 32, 33 */ \
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{0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
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/* ALL_REGS : 0-100 */ \
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{0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
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}
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#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
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@ -869,14 +914,20 @@ enum reg_class
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#define LOCAL_LABEL_PREFIX "."
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#define REGISTER_NAMES \
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{ \
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"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
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#define REGISTER_NAMES \
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{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
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"$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
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"$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
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"$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
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"$AP", \
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"$SFP" \
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"$AP", "$SFP", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \
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"NA", "NA", "NA", "NA", "NA" \
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}
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/* Output normal jump table entry. */
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