re PR target/49030 (ICE in get_arm_condition_code, at config/arm/arm.c:17180)
gcc/ PR target/49030 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare. * config/arm/arm.c (maybe_get_arm_condition_code): New function, reusing the old code from get_arm_condition_code. Return ARM_NV for invalid comparison codes. (get_arm_condition_code): Redefine in terms of maybe_get_arm_condition_code. * config/arm/predicates.md (arm_comparison_operator): Use maybe_get_arm_condition_code. gcc/testsuite/ PR target/49030 * gcc.dg/torture/pr49030.c: New test. From-SVN: r178636
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@ -1,3 +1,15 @@
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2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
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PR target/49030
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* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
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* config/arm/arm.c (maybe_get_arm_condition_code): New function,
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reusing the old code from get_arm_condition_code. Return ARM_NV
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for invalid comparison codes.
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(get_arm_condition_code): Redefine in terms of
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maybe_get_arm_condition_code.
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* config/arm/predicates.md (arm_comparison_operator): Use
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maybe_get_arm_condition_code.
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2011-09-07 Richard Guenther <rguenther@suse.de>
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2011-09-07 Richard Guenther <rguenther@suse.de>
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* tree-ssa-forwprop.c (forward_propagate_into_gimple_cond):
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* tree-ssa-forwprop.c (forward_propagate_into_gimple_cond):
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@ -184,6 +184,7 @@ extern int is_called_in_ARM_mode (tree);
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#endif
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#endif
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extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
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extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
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#ifdef RTX_CODE
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#ifdef RTX_CODE
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extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
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extern void thumb1_final_prescan_insn (rtx);
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extern void thumb1_final_prescan_insn (rtx);
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extern void thumb2_final_prescan_insn (rtx);
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extern void thumb2_final_prescan_insn (rtx);
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extern const char *thumb_load_double_from_address (rtx *);
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extern const char *thumb_load_double_from_address (rtx *);
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@ -17595,10 +17595,10 @@ arm_elf_asm_destructor (rtx symbol, int priority)
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decremented/zeroed by arm_asm_output_opcode as the insns are output. */
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decremented/zeroed by arm_asm_output_opcode as the insns are output. */
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/* Returns the index of the ARM condition code string in
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/* Returns the index of the ARM condition code string in
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`arm_condition_codes'. COMPARISON should be an rtx like
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`arm_condition_codes', or ARM_NV if the comparison is invalid.
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`(eq (...) (...))'. */
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COMPARISON should be an rtx like `(eq (...) (...))'. */
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static enum arm_cond_code
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enum arm_cond_code
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get_arm_condition_code (rtx comparison)
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maybe_get_arm_condition_code (rtx comparison)
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{
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{
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enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
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enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
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enum arm_cond_code code;
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enum arm_cond_code code;
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@ -17622,11 +17622,11 @@ get_arm_condition_code (rtx comparison)
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case CC_DLTUmode: code = ARM_CC;
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case CC_DLTUmode: code = ARM_CC;
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dominance:
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dominance:
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gcc_assert (comp_code == EQ || comp_code == NE);
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if (comp_code == EQ)
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if (comp_code == EQ)
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return ARM_INVERSE_CONDITION_CODE (code);
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return ARM_INVERSE_CONDITION_CODE (code);
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return code;
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if (comp_code == NE)
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return code;
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return ARM_NV;
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case CC_NOOVmode:
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case CC_NOOVmode:
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switch (comp_code)
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switch (comp_code)
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@ -17635,7 +17635,7 @@ get_arm_condition_code (rtx comparison)
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case EQ: return ARM_EQ;
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case EQ: return ARM_EQ;
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case GE: return ARM_PL;
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case GE: return ARM_PL;
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case LT: return ARM_MI;
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case LT: return ARM_MI;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_Zmode:
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case CC_Zmode:
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@ -17643,7 +17643,7 @@ get_arm_condition_code (rtx comparison)
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{
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{
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case NE: return ARM_NE;
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case NE: return ARM_NE;
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case EQ: return ARM_EQ;
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case EQ: return ARM_EQ;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_Nmode:
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case CC_Nmode:
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@ -17651,7 +17651,7 @@ get_arm_condition_code (rtx comparison)
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{
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{
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case NE: return ARM_MI;
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case NE: return ARM_MI;
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case EQ: return ARM_PL;
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case EQ: return ARM_PL;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CCFPEmode:
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case CCFPEmode:
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@ -17676,7 +17676,7 @@ get_arm_condition_code (rtx comparison)
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/* UNEQ and LTGT do not have a representation. */
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/* UNEQ and LTGT do not have a representation. */
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case UNEQ: /* Fall through. */
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case UNEQ: /* Fall through. */
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case LTGT: /* Fall through. */
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case LTGT: /* Fall through. */
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_SWPmode:
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case CC_SWPmode:
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@ -17692,7 +17692,7 @@ get_arm_condition_code (rtx comparison)
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case GTU: return ARM_CC;
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case GTU: return ARM_CC;
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case LEU: return ARM_CS;
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case LEU: return ARM_CS;
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case LTU: return ARM_HI;
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case LTU: return ARM_HI;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_Cmode:
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case CC_Cmode:
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@ -17700,7 +17700,7 @@ get_arm_condition_code (rtx comparison)
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{
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{
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case LTU: return ARM_CS;
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case LTU: return ARM_CS;
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case GEU: return ARM_CC;
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case GEU: return ARM_CC;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_CZmode:
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case CC_CZmode:
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@ -17712,7 +17712,7 @@ get_arm_condition_code (rtx comparison)
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case GTU: return ARM_HI;
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case GTU: return ARM_HI;
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case LEU: return ARM_LS;
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case LEU: return ARM_LS;
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case LTU: return ARM_CC;
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case LTU: return ARM_CC;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CC_NCVmode:
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case CC_NCVmode:
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@ -17722,7 +17722,7 @@ get_arm_condition_code (rtx comparison)
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case LT: return ARM_LT;
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case LT: return ARM_LT;
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case GEU: return ARM_CS;
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case GEU: return ARM_CS;
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case LTU: return ARM_CC;
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case LTU: return ARM_CC;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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case CCmode:
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case CCmode:
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@ -17738,13 +17738,22 @@ get_arm_condition_code (rtx comparison)
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case GTU: return ARM_HI;
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case GTU: return ARM_HI;
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case LEU: return ARM_LS;
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case LEU: return ARM_LS;
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case LTU: return ARM_CC;
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case LTU: return ARM_CC;
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default: gcc_unreachable ();
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default: return ARM_NV;
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}
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}
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
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static enum arm_cond_code
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get_arm_condition_code (rtx comparison)
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{
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enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
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gcc_assert (code != ARM_NV);
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return code;
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}
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/* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
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/* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
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instructions. */
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instructions. */
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void
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void
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@ -249,10 +249,9 @@
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;; True for integer comparisons and, if FP is active, for comparisons
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;; True for integer comparisons and, if FP is active, for comparisons
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;; other than LTGT or UNEQ.
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;; other than LTGT or UNEQ.
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(define_special_predicate "arm_comparison_operator"
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(define_special_predicate "arm_comparison_operator"
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(ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
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(and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
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(and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
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unordered,ordered,unlt,unle,unge,ungt")
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&& (TARGET_FPA || TARGET_VFP)")
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(match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
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(match_code "unordered,ordered,unlt,unle,unge,ungt"))))
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(define_special_predicate "lt_ge_comparison_operator"
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(define_special_predicate "lt_ge_comparison_operator"
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(match_code "lt,ge"))
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(match_code "lt,ge"))
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@ -1,3 +1,8 @@
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2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
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PR target/49030
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* gcc.dg/torture/pr49030.c: New test.
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2011-09-07 Janus Weil <janus@gcc.gnu.org>
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2011-09-07 Janus Weil <janus@gcc.gnu.org>
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PR fortran/50288
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PR fortran/50288
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19
gcc/testsuite/gcc.dg/torture/pr49030.c
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19
gcc/testsuite/gcc.dg/torture/pr49030.c
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@ -0,0 +1,19 @@
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void
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sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
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unsigned long dst_skip)
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{
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long long y;
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while (nsamples--)
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{
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y = (long long) (*src * 8388608.0f) << 8;
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if (y > 2147483647) {
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*(int *) dst = 2147483647;
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} else if (y < -2147483647 - 1) {
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*(int *) dst = -2147483647 - 1;
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} else {
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*(int *) dst = (int) y;
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}
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dst += dst_skip;
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src++;
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}
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}
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