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i386.md (prefix_data16, prefix_rep): Set to 0 for TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.

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* config/i386/i386.md (prefix_data16, prefix_rep): Set to 0 for
	TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.
	(prefix_rex): For UNIT_MMX don't imply the prefix by default
	if MODE_DI.
	(prefix_extra): Default to 2 for TYPE_SSE{MULADD,4ARG} and
	to 1 for TYPE_SSE{IADD1,CVT1}.
	(prefix_vex_imm8): Removed.
	(length_vex): Only pass 1 as second argument to
	ix86_attr_length_vex_default if prefix_extra is 0.
	(modrm): For TYPE_INCDEC only set to 0 if not TARGET_64BIT.
	(length): For prefix vex computation use length_immediate
	attribute instead of prefix_vex_imm8.
	(cmpqi_ext_3_insn, cmpqi_ext_3_insn_rex64,
	addqi_ext_1, addqi_ext_1_rex64, *testqi_ext_0, andqi_ext_0,
	*andqi_ext_0_cc, *iorqi_ext_0, *xorqi_ext_0, *xorqi_cc_ext_1,
	*xorqi_cc_ext_1_rex64): Override modrm attribute to 1.
	(extendsidi2_rex64, extendhidi2, extendqidi2, extendhisi2,
	*extendhisi2_zext, extendqihi2, extendqisi2, *extendqisi2_zext): Emit
	a space in between the operands.
	(*anddi_1_rex64, *andsi_1): Likewise.  Override prefix_rex to 1
	if one operand is 0xff and the other one si, di, bp or sp.
	(*andhi_1): Override prefix_rex to 1 if one operand is 0xff and the
	other one si, di, bp or sp.
	(*btsq, *btrq, *btcq, *btdi_rex64, *btsi): Add mode attribute.
	(*ffssi_1, *ffsdi_1, ctzsi2, ctzdi2): Add
	type and mode attributes.
	(*bsr, *bsr_rex64, *bsrhi): Add type attribute.
	(*cmpfp_i_mixed, *cmpfp_iu_mixed): For TYPE_SSECOMI, clear
	prefix_rep attribute and set prefix_data16 attribute iff MODE_DF.
	(*cmpfp_i_sse, *cmpfp_iu_sse): Clear prefix_rep attribute and set
	prefix_data16 attribute iff MODE_DF.
	(*movsi_1): For TYPE_SSEMOV MODE_SI set prefix_data16 attribute.
	(fix_trunc<mode>di_sse): Set prefix_rex attribute.
	(*adddi_4_rex64, *addsi_4): Use const128_operand instead of
	constm128_operand in length_immediate computation.
	(*addhi_4): Likewise.  Fix mode attribute to MODE_HI.
	(anddi_1_rex64): Use movzbl/movzwl instead of movzbq/movzwq.
	(*avx_ashlti3, sse2_ashlti3, *avx_lshrti3, sse2_lshrti3): Set
	length_immediate attribute to 1.
	(x86_fnstsw_1, x86_fnstcw_1, x86_fldcw_1): Fix length attribute.
	(*movdi_1_rex64): Override prefix_rex or prefix_data16 attributes
	for certain alternatives.
	(*movdf_nointeger, *movdf_integer_rex64, *movdf_integer): Override
	prefix_data16 attribute if MODE_V1DF.
	(*avx_setcc<mode>, *sse_setcc<mode>, *sse5_setcc<mode>): Set
	length_immediate to 1.
	(set_got_rex64, set_rip_rex64): Remove length attribute, set
	length_address to 4, set mode attribute to MODE_DI.
	(set_got_offset_rex64): Likewise.  Set length_immediate to 0.
	(fxam<mode>2_i387): Set length attribute to 4.
	(*prefetch_sse, *prefetch_sse_rex, *prefetch_3dnow,
	*prefetch_3dnow_rex): Override length_address attribute.
	(sse4_2_crc32<mode>): Override prefix_data16 and prefix_rex
	attributes.
	* config/i386/predicates.md (ext_QIreg_nomode_operand): New predicate.
	(constm128_operand): Removed.
	* config/i386/i386.c (memory_address_length): For
	disp && !index && !base in 64-bit mode account for SIB byte if
	print_operand_address can't optimize disp32 into disp32(%rip)
	and UNSPEC doesn't imply (%rip) addressing.  Add 1 to length
	for fs: or gs: segment.
	(ix86_attr_length_immediate_default): When checking if shortform
	is possible, truncate immediate to the length of the non-shortened
	immediate.
	(ix86_attr_length_address_default): Ignore MEM_P operands
	with X constraint.
	(ix86_attr_length_vex_default): Only check for DImode on
	GENERAL_REG_P operands.
	* config/i386/sse.md (<sse>_comi, <sse>_ucomi): Clear
	prefix_rep attribute, set prefix_data16 attribute iff MODE_DF.
	(sse_cvttps2pi): Clear prefix_rep attribute.
	(sse2_cvttps2dq, *sse2_cvtpd2dq, sse2_cvtps2pd): Clear prefix_data16
	attribute.
	(*sse2_cvttpd2dq): Don't clear prefix_rep attribute.
	(*avx_ashr<mode>3, ashr<mode>3, *avx_lshr<mode>3, lshr<mode>3,
	*avx_ashl<mode>3, ashl<mode>3): Set length_immediate attribute to 1
	iff operand 2 is const_int_operand.
	(*vec_dupv4si, avx_shufpd256_1, *avx_shufpd_<mode>,
	sse2_shufpd_<mode>): Set length_immediate attribute to 1.
	(sse2_pshufd_1): Likewise.  Set prefix attribute to maybe_vex
	instead of vex.
	(sse2_pshuflw_1, sse2_pshufhw_1): Set length_immediate to 1 and clear
	prefix_data16.
	(sse2_unpckhpd, sse2_unpcklpd, sse2_storehpd, *vec_concatv2df): Set
	prefix_data16 attribute for movlpd and movhpd instructions.
	(sse2_loadhpd, sse2_loadlpd, sse2_movsd): Likewise.  Override
	length_immediate for shufpd instruction.
	(sse2_movntsi, sse3_lddqu): Clear prefix_data16 attribute.
	(avx_cmpp<avxmodesuffixf2c><mode>3,
	avx_cmps<ssemodesuffixf2c><mode>3, *avx_maskcmp<mode>3,
	<sse>_maskcmp<mode>3, <sse>_vmmaskcmp<mode>3,
	avx_shufps256_1, *avx_shufps_<mode>, sse_shufps_<mode>,
	*vec_dupv4sf_avx, *vec_dupv4sf): Set
	length_immediate attribute to 1.
	(*avx_cvtsi2ssq, *avx_cvtsi2sdq): Set length_vex attribute to 4.
	(sse_cvtsi2ssq, sse2_cvtsi2sdq): Set prefix_rex attribute to 1.
	(sse2_cvtpi2pd, sse_loadlps, sse2_storelpd): Override
	prefix_data16 attribute for the first alternative to 1.
	(*avx_loadlps): Override length_immediate for the first alternative.
	(*vec_concatv2sf_avx): Override length_immediate and prefix_extra
	attributes for second alternative.
	(*vec_concatv2sf_sse4_1): Override length_immediate and
	prefix_data16 attributes for second alternative.
	(*vec_setv4sf_avx, *avx_insertps, vec_extract_lo_<mode>,
	vec_extract_hi_<mode>, vec_extract_lo_v16hi,
	vec_extract_hi_v16hi, vec_extract_lo_v32qi,
	vec_extract_hi_v32qi): Set prefix_extra and length_immediate to 1.
	(*vec_setv4sf_sse4_1, sse4_1_insertps, *sse4_1_extractps): Set
	prefix_data16 and length_immediate to 1.
	(*avx_mulv2siv2di3, *avx_mulv4si3, sse4_2_gtv2di3): Set prefix_extra
	to 1.
	(*avx_<code><mode>3, *avx_eq<mode>3, *avx_gt<mode>3): Set
	prefix_extra attribute for variants that don't have 0f prefix
	alone.
	(*avx_pinsr<ssevecsize>): Likewise.  Set length_immediate to 1.
	(*sse4_1_pinsrb, *sse2_pinsrw, *sse4_1_pinsrd, *sse4_1_pextrb,
	*sse4_1_pextrb_memory, *sse2_pextrw, *sse4_1_pextrw_memory,
	*sse4_1_pextrd): Set length_immediate to 1.
	(*sse4_1_pinsrd): Likewise.  Set prefix_extra to 1.
	(*sse4_1_pinsrq, *sse4_1_pextrq): Set prefix_rex and length_immediate
	to 1.
	(*vec_extractv2di_1_rex64_avx, *vec_extractv2di_1_rex64,
	*vec_extractv2di_1_avx, *vec_extractv2di_1_sse2): Override
	length_immediate to 1 for second alternative.
	(*vec_concatv2si_avx, *vec_concatv2di_rex64_avx): Override
	prefix_extra and length_immediate attributes for the first
	alternative.
	(vec_concatv2si_sse4_1): Override length_immediate to 1 for the
	first alternative.
	(*vec_concatv2di_rex64_sse4_1): Likewise.  Override prefix_rex
	to 1 for the first and third alternative.
	(*vec_concatv2di_rex64_sse): Override prefix_rex to 1 for the second
	alternative.
	(*sse2_maskmovdqu, *sse2_maskmovdqu_rex64): Override length_vex
	attribute.
	(*sse_sfence, sse2_mfence, sse2_lfence): Override length_address
	attribute to 0.
	(*avx_phaddwv8hi3, *avx_phadddv4si3, *avx_phaddswv8hi3,
	*avx_phsubwv8hi3, *avx_phsubdv4si3, *avx_phsubswv8hi,
	*avx_pmaddubsw128, *avx_pmulhrswv8hi3, *avx_pshufbv16qi3,
	*avx_psign<mode>3): Set prefix_extra attribute to 1.
	(ssse3_phaddwv4hi3, ssse3_phadddv2si3, ssse3_phaddswv4hi3,
	ssse3_phsubwv4hi3, ssse3_phsubdv2si3, ssse3_phsubswv4hi3,
	ssse3_pmaddubsw, *ssse3_pmulhrswv4hi, ssse3_pshufbv8qi3,
	ssse3_psign<mode>3): Override prefix_rex attribute.
	(*avx_palignrti): Override prefix_extra and length_immediate
	to 1.
	(ssse3_palignrti): Override length_immediate to 1.
	(ssse3_palignrdi): Override length_immediate to 1, override
	prefix_rex attribute.
	(abs<mode>2): Override prefix_rep to 0, override prefix_rex
	attribute.
	(sse4a_extrqi): Override length_immediate to 2.
	(sse4a_insertqi): Likewise.  Override prefix_data16 to 0.
	(sse4a_insertq): Override prefix_data16 to 0.
	(avx_blendp<avxmodesuffixf2c><avxmodesuffix>,
	avx_blendvp<avxmodesuffixf2c><avxmodesuffix>,
	avx_dpp<avxmodesuffixf2c><avxmodesuffix>, *avx_mpsadbw,
	*avx_pblendvb, *avx_pblendw, avx_roundp<avxmodesuffixf2c>256,
	avx_rounds<avxmodesuffixf2c>256): Override prefix_extra
	and length_immediate to 1.
	(sse4_1_blendp<ssemodesuffixf2c>, sse4_1_dpp<ssemodesuffixf2c>,
	sse4_2_pcmpestr, sse4_2_pcmpestri, sse4_2_pcmpestrm,
	sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, sse4_2_pcmpistri,
	sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Override prefix_data16
	and length_immediate to 1.
	(sse4_1_blendvp<ssemodesuffixf2c>): Override prefix_data16 to 1.
	(sse4_1_mpsadbw, sse4_1_pblendw): Override length_immediate to 1.
	(*avx_packusdw, avx_vtestp<avxmodesuffixf2c><avxmodesuffix>,
	avx_ptest256): Override prefix_extra to 1.
	(sse4_1_roundp<ssemodesuffixf2c>, sse4_1_rounds<ssemodesuffixf2c>):
	Override prefix_data16 and length_immediate to 1.
	(sse5_pperm_zero_v16qi_v8hi, sse5_pperm_sign_v16qi_v8hi,
	sse5_pperm_zero_v8hi_v4si, sse5_pperm_sign_v8hi_v4si,
	sse5_pperm_zero_v4si_v2di, sse5_pperm_sign_v4si_v2di,
	sse5_vrotl<mode>3, sse5_ashl<mode>3, sse5_lshl<mode>3): Override
	prefix_data16 to 0 and prefix_extra to 2.
	(sse5_rotl<mode>3, sse5_rotr<mode>3): Override length_immediate to 1.
	(sse5_frcz<mode>2, sse5_vmfrcz<mode>2): Don't override prefix_extra
	attribute.
	(*sse5_vmmaskcmp<mode>3, sse5_com_tf<mode>3,
	sse5_maskcmp<mode>3, sse5_maskcmp<mode>3, sse5_maskcmp_uns<mode>3):
	Override prefix_data16 and prefix_rep to 0, length_immediate to 1
	and prefix_extra to 2.
	(sse5_maskcmp_uns2<mode>3, sse5_pcom_tf<mode>3): Override
	prefix_data16 to 0, length_immediate to 1 and prefix_extra to 2.
	(*avx_aesenc, *avx_aesenclast, *avx_aesdec, *avx_aesdeclast,
	avx_vpermilvar<mode>3,
	avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>,
	avx_vbroadcastss256, avx_vbroadcastf128_p<avxmodesuffixf2c>256,
	avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>,
	avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>):
	Override prefix_extra to 1.
	(aeskeygenassist, pclmulqdq): Override length_immediate to 1.
	(*vpclmulqdq, avx_vpermil<mode>, avx_vperm2f128<mode>3,
	vec_set_lo_<mode>, vec_set_hi_<mode>, vec_set_lo_v16hi,
	vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Override
	prefix_extra and length_immediate to 1.
	(*avx_vzeroall, avx_vzeroupper, avx_vzeroupper_rex64): Override
	modrm to 0.
	(*vec_concat<mode>_avx): Override prefix_extra and length_immediate
	to 1 for the first alternative.
	* config/i386/mmx.md (*mov<mode>_internal_rex64): Override
	prefix_rep, prefix_data16 and/or prefix_rex attributes in certain
	cases.
	(*mov<mode>_internal_avx, *movv2sf_internal_rex64,
	*movv2sf_internal_avx, *movv2sf_internal): Override
	prefix_rep attribute for certain alternatives.
	(*mov<mode>_internal): Override prefix_rep or prefix_data16
	attributes for certain alternatives.
	(*movv2sf_internal_rex64_avx): Override prefix_rep and length_vex
	attributes for certain alternatives.
	(*mmx_addv2sf3, *mmx_subv2sf3, *mmx_mulv2sf3,
	*mmx_<code>v2sf3_finite, *mmx_<code>v2sf3, mmx_rcpv2sf2,
	mmx_rcpit1v2sf3, mmx_rcpit2v2sf3, mmx_rsqrtv2sf2, mmx_rsqit1v2sf3,
	mmx_haddv2sf3, mmx_hsubv2sf3, mmx_addsubv2sf3,
	*mmx_eqv2sf3, mmx_gtv2sf3, mmx_gev2sf3, mmx_pf2id, mmx_pf2iw,
	mmx_pi2fw, mmx_floatv2si2, mmx_pswapdv2sf2, *mmx_pmulhrwv4hi3,
	mmx_pswapdv2si2): Set prefix_extra attribute to 1.
	(mmx_ashr<mode>3, mmx_lshr<mode>3, mmx_ashl<mode>3): Set
	length_immediate to 1 if operand 2 is const_int_operand.
	(*mmx_pinsrw, mmx_pextrw, mmx_pshufw_1, *vec_dupv4hi,
	*vec_extractv2si_1): Set length_immediate
	attribute to 1.
	(*mmx_uavgv8qi3): Override prefix_extra attribute to 1 if
	using old 3DNOW insn rather than SSE/3DNOW_A.
	(mmx_emms, mmx_femms): Clear modrm attribute.

From-SVN: r147981
This commit is contained in:
Jakub Jelinek 2009-05-29 18:59:31 +02:00 committed by Jakub Jelinek
parent 0674b9d090
commit 725fd454ae
6 changed files with 902 additions and 86 deletions
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@ -1,3 +1,233 @@
2009-05-29 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.md (prefix_data16, prefix_rep): Set to 0 for
TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.
(prefix_rex): For UNIT_MMX don't imply the prefix by default
if MODE_DI.
(prefix_extra): Default to 2 for TYPE_SSE{MULADD,4ARG} and
to 1 for TYPE_SSE{IADD1,CVT1}.
(prefix_vex_imm8): Removed.
(length_vex): Only pass 1 as second argument to
ix86_attr_length_vex_default if prefix_extra is 0.
(modrm): For TYPE_INCDEC only set to 0 if not TARGET_64BIT.
(length): For prefix vex computation use length_immediate
attribute instead of prefix_vex_imm8.
(cmpqi_ext_3_insn, cmpqi_ext_3_insn_rex64,
addqi_ext_1, addqi_ext_1_rex64, *testqi_ext_0, andqi_ext_0,
*andqi_ext_0_cc, *iorqi_ext_0, *xorqi_ext_0, *xorqi_cc_ext_1,
*xorqi_cc_ext_1_rex64): Override modrm attribute to 1.
(extendsidi2_rex64, extendhidi2, extendqidi2, extendhisi2,
*extendhisi2_zext, extendqihi2, extendqisi2, *extendqisi2_zext): Emit
a space in between the operands.
(*anddi_1_rex64, *andsi_1): Likewise. Override prefix_rex to 1
if one operand is 0xff and the other one si, di, bp or sp.
(*andhi_1): Override prefix_rex to 1 if one operand is 0xff and the
other one si, di, bp or sp.
(*btsq, *btrq, *btcq, *btdi_rex64, *btsi): Add mode attribute.
(*ffssi_1, *ffsdi_1, ctzsi2, ctzdi2): Add
type and mode attributes.
(*bsr, *bsr_rex64, *bsrhi): Add type attribute.
(*cmpfp_i_mixed, *cmpfp_iu_mixed): For TYPE_SSECOMI, clear
prefix_rep attribute and set prefix_data16 attribute iff MODE_DF.
(*cmpfp_i_sse, *cmpfp_iu_sse): Clear prefix_rep attribute and set
prefix_data16 attribute iff MODE_DF.
(*movsi_1): For TYPE_SSEMOV MODE_SI set prefix_data16 attribute.
(fix_trunc<mode>di_sse): Set prefix_rex attribute.
(*adddi_4_rex64, *addsi_4): Use const128_operand instead of
constm128_operand in length_immediate computation.
(*addhi_4): Likewise. Fix mode attribute to MODE_HI.
(anddi_1_rex64): Use movzbl/movzwl instead of movzbq/movzwq.
(*avx_ashlti3, sse2_ashlti3, *avx_lshrti3, sse2_lshrti3): Set
length_immediate attribute to 1.
(x86_fnstsw_1, x86_fnstcw_1, x86_fldcw_1): Fix length attribute.
(*movdi_1_rex64): Override prefix_rex or prefix_data16 attributes
for certain alternatives.
(*movdf_nointeger, *movdf_integer_rex64, *movdf_integer): Override
prefix_data16 attribute if MODE_V1DF.
(*avx_setcc<mode>, *sse_setcc<mode>, *sse5_setcc<mode>): Set
length_immediate to 1.
(set_got_rex64, set_rip_rex64): Remove length attribute, set
length_address to 4, set mode attribute to MODE_DI.
(set_got_offset_rex64): Likewise. Set length_immediate to 0.
(fxam<mode>2_i387): Set length attribute to 4.
(*prefetch_sse, *prefetch_sse_rex, *prefetch_3dnow,
*prefetch_3dnow_rex): Override length_address attribute.
(sse4_2_crc32<mode>): Override prefix_data16 and prefix_rex
attributes.
* config/i386/predicates.md (ext_QIreg_nomode_operand): New predicate.
(constm128_operand): Removed.
* config/i386/i386.c (memory_address_length): For
disp && !index && !base in 64-bit mode account for SIB byte if
print_operand_address can't optimize disp32 into disp32(%rip)
and UNSPEC doesn't imply (%rip) addressing. Add 1 to length
for fs: or gs: segment.
(ix86_attr_length_immediate_default): When checking if shortform
is possible, truncate immediate to the length of the non-shortened
immediate.
(ix86_attr_length_address_default): Ignore MEM_P operands
with X constraint.
(ix86_attr_length_vex_default): Only check for DImode on
GENERAL_REG_P operands.
* config/i386/sse.md (<sse>_comi, <sse>_ucomi): Clear
prefix_rep attribute, set prefix_data16 attribute iff MODE_DF.
(sse_cvttps2pi): Clear prefix_rep attribute.
(sse2_cvttps2dq, *sse2_cvtpd2dq, sse2_cvtps2pd): Clear prefix_data16
attribute.
(*sse2_cvttpd2dq): Don't clear prefix_rep attribute.
(*avx_ashr<mode>3, ashr<mode>3, *avx_lshr<mode>3, lshr<mode>3,
*avx_ashl<mode>3, ashl<mode>3): Set length_immediate attribute to 1
iff operand 2 is const_int_operand.
(*vec_dupv4si, avx_shufpd256_1, *avx_shufpd_<mode>,
sse2_shufpd_<mode>): Set length_immediate attribute to 1.
(sse2_pshufd_1): Likewise. Set prefix attribute to maybe_vex
instead of vex.
(sse2_pshuflw_1, sse2_pshufhw_1): Set length_immediate to 1 and clear
prefix_data16.
(sse2_unpckhpd, sse2_unpcklpd, sse2_storehpd, *vec_concatv2df): Set
prefix_data16 attribute for movlpd and movhpd instructions.
(sse2_loadhpd, sse2_loadlpd, sse2_movsd): Likewise. Override
length_immediate for shufpd instruction.
(sse2_movntsi, sse3_lddqu): Clear prefix_data16 attribute.
(avx_cmpp<avxmodesuffixf2c><mode>3,
avx_cmps<ssemodesuffixf2c><mode>3, *avx_maskcmp<mode>3,
<sse>_maskcmp<mode>3, <sse>_vmmaskcmp<mode>3,
avx_shufps256_1, *avx_shufps_<mode>, sse_shufps_<mode>,
*vec_dupv4sf_avx, *vec_dupv4sf): Set
length_immediate attribute to 1.
(*avx_cvtsi2ssq, *avx_cvtsi2sdq): Set length_vex attribute to 4.
(sse_cvtsi2ssq, sse2_cvtsi2sdq): Set prefix_rex attribute to 1.
(sse2_cvtpi2pd, sse_loadlps, sse2_storelpd): Override
prefix_data16 attribute for the first alternative to 1.
(*avx_loadlps): Override length_immediate for the first alternative.
(*vec_concatv2sf_avx): Override length_immediate and prefix_extra
attributes for second alternative.
(*vec_concatv2sf_sse4_1): Override length_immediate and
prefix_data16 attributes for second alternative.
(*vec_setv4sf_avx, *avx_insertps, vec_extract_lo_<mode>,
vec_extract_hi_<mode>, vec_extract_lo_v16hi,
vec_extract_hi_v16hi, vec_extract_lo_v32qi,
vec_extract_hi_v32qi): Set prefix_extra and length_immediate to 1.
(*vec_setv4sf_sse4_1, sse4_1_insertps, *sse4_1_extractps): Set
prefix_data16 and length_immediate to 1.
(*avx_mulv2siv2di3, *avx_mulv4si3, sse4_2_gtv2di3): Set prefix_extra
to 1.
(*avx_<code><mode>3, *avx_eq<mode>3, *avx_gt<mode>3): Set
prefix_extra attribute for variants that don't have 0f prefix
alone.
(*avx_pinsr<ssevecsize>): Likewise. Set length_immediate to 1.
(*sse4_1_pinsrb, *sse2_pinsrw, *sse4_1_pinsrd, *sse4_1_pextrb,
*sse4_1_pextrb_memory, *sse2_pextrw, *sse4_1_pextrw_memory,
*sse4_1_pextrd): Set length_immediate to 1.
(*sse4_1_pinsrd): Likewise. Set prefix_extra to 1.
(*sse4_1_pinsrq, *sse4_1_pextrq): Set prefix_rex and length_immediate
to 1.
(*vec_extractv2di_1_rex64_avx, *vec_extractv2di_1_rex64,
*vec_extractv2di_1_avx, *vec_extractv2di_1_sse2): Override
length_immediate to 1 for second alternative.
(*vec_concatv2si_avx, *vec_concatv2di_rex64_avx): Override
prefix_extra and length_immediate attributes for the first
alternative.
(vec_concatv2si_sse4_1): Override length_immediate to 1 for the
first alternative.
(*vec_concatv2di_rex64_sse4_1): Likewise. Override prefix_rex
to 1 for the first and third alternative.
(*vec_concatv2di_rex64_sse): Override prefix_rex to 1 for the second
alternative.
(*sse2_maskmovdqu, *sse2_maskmovdqu_rex64): Override length_vex
attribute.
(*sse_sfence, sse2_mfence, sse2_lfence): Override length_address
attribute to 0.
(*avx_phaddwv8hi3, *avx_phadddv4si3, *avx_phaddswv8hi3,
*avx_phsubwv8hi3, *avx_phsubdv4si3, *avx_phsubswv8hi,
*avx_pmaddubsw128, *avx_pmulhrswv8hi3, *avx_pshufbv16qi3,
*avx_psign<mode>3): Set prefix_extra attribute to 1.
(ssse3_phaddwv4hi3, ssse3_phadddv2si3, ssse3_phaddswv4hi3,
ssse3_phsubwv4hi3, ssse3_phsubdv2si3, ssse3_phsubswv4hi3,
ssse3_pmaddubsw, *ssse3_pmulhrswv4hi, ssse3_pshufbv8qi3,
ssse3_psign<mode>3): Override prefix_rex attribute.
(*avx_palignrti): Override prefix_extra and length_immediate
to 1.
(ssse3_palignrti): Override length_immediate to 1.
(ssse3_palignrdi): Override length_immediate to 1, override
prefix_rex attribute.
(abs<mode>2): Override prefix_rep to 0, override prefix_rex
attribute.
(sse4a_extrqi): Override length_immediate to 2.
(sse4a_insertqi): Likewise. Override prefix_data16 to 0.
(sse4a_insertq): Override prefix_data16 to 0.
(avx_blendp<avxmodesuffixf2c><avxmodesuffix>,
avx_blendvp<avxmodesuffixf2c><avxmodesuffix>,
avx_dpp<avxmodesuffixf2c><avxmodesuffix>, *avx_mpsadbw,
*avx_pblendvb, *avx_pblendw, avx_roundp<avxmodesuffixf2c>256,
avx_rounds<avxmodesuffixf2c>256): Override prefix_extra
and length_immediate to 1.
(sse4_1_blendp<ssemodesuffixf2c>, sse4_1_dpp<ssemodesuffixf2c>,
sse4_2_pcmpestr, sse4_2_pcmpestri, sse4_2_pcmpestrm,
sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, sse4_2_pcmpistri,
sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Override prefix_data16
and length_immediate to 1.
(sse4_1_blendvp<ssemodesuffixf2c>): Override prefix_data16 to 1.
(sse4_1_mpsadbw, sse4_1_pblendw): Override length_immediate to 1.
(*avx_packusdw, avx_vtestp<avxmodesuffixf2c><avxmodesuffix>,
avx_ptest256): Override prefix_extra to 1.
(sse4_1_roundp<ssemodesuffixf2c>, sse4_1_rounds<ssemodesuffixf2c>):
Override prefix_data16 and length_immediate to 1.
(sse5_pperm_zero_v16qi_v8hi, sse5_pperm_sign_v16qi_v8hi,
sse5_pperm_zero_v8hi_v4si, sse5_pperm_sign_v8hi_v4si,
sse5_pperm_zero_v4si_v2di, sse5_pperm_sign_v4si_v2di,
sse5_vrotl<mode>3, sse5_ashl<mode>3, sse5_lshl<mode>3): Override
prefix_data16 to 0 and prefix_extra to 2.
(sse5_rotl<mode>3, sse5_rotr<mode>3): Override length_immediate to 1.
(sse5_frcz<mode>2, sse5_vmfrcz<mode>2): Don't override prefix_extra
attribute.
(*sse5_vmmaskcmp<mode>3, sse5_com_tf<mode>3,
sse5_maskcmp<mode>3, sse5_maskcmp<mode>3, sse5_maskcmp_uns<mode>3):
Override prefix_data16 and prefix_rep to 0, length_immediate to 1
and prefix_extra to 2.
(sse5_maskcmp_uns2<mode>3, sse5_pcom_tf<mode>3): Override
prefix_data16 to 0, length_immediate to 1 and prefix_extra to 2.
(*avx_aesenc, *avx_aesenclast, *avx_aesdec, *avx_aesdeclast,
avx_vpermilvar<mode>3,
avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>,
avx_vbroadcastss256, avx_vbroadcastf128_p<avxmodesuffixf2c>256,
avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>,
avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>):
Override prefix_extra to 1.
(aeskeygenassist, pclmulqdq): Override length_immediate to 1.
(*vpclmulqdq, avx_vpermil<mode>, avx_vperm2f128<mode>3,
vec_set_lo_<mode>, vec_set_hi_<mode>, vec_set_lo_v16hi,
vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Override
prefix_extra and length_immediate to 1.
(*avx_vzeroall, avx_vzeroupper, avx_vzeroupper_rex64): Override
modrm to 0.
(*vec_concat<mode>_avx): Override prefix_extra and length_immediate
to 1 for the first alternative.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Override
prefix_rep, prefix_data16 and/or prefix_rex attributes in certain
cases.
(*mov<mode>_internal_avx, *movv2sf_internal_rex64,
*movv2sf_internal_avx, *movv2sf_internal): Override
prefix_rep attribute for certain alternatives.
(*mov<mode>_internal): Override prefix_rep or prefix_data16
attributes for certain alternatives.
(*movv2sf_internal_rex64_avx): Override prefix_rep and length_vex
attributes for certain alternatives.
(*mmx_addv2sf3, *mmx_subv2sf3, *mmx_mulv2sf3,
*mmx_<code>v2sf3_finite, *mmx_<code>v2sf3, mmx_rcpv2sf2,
mmx_rcpit1v2sf3, mmx_rcpit2v2sf3, mmx_rsqrtv2sf2, mmx_rsqit1v2sf3,
mmx_haddv2sf3, mmx_hsubv2sf3, mmx_addsubv2sf3,
*mmx_eqv2sf3, mmx_gtv2sf3, mmx_gev2sf3, mmx_pf2id, mmx_pf2iw,
mmx_pi2fw, mmx_floatv2si2, mmx_pswapdv2sf2, *mmx_pmulhrwv4hi3,
mmx_pswapdv2si2): Set prefix_extra attribute to 1.
(mmx_ashr<mode>3, mmx_lshr<mode>3, mmx_ashl<mode>3): Set
length_immediate to 1 if operand 2 is const_int_operand.
(*mmx_pinsrw, mmx_pextrw, mmx_pshufw_1, *vec_dupv4hi,
*vec_extractv2si_1): Set length_immediate
attribute to 1.
(*mmx_uavgv8qi3): Override prefix_extra attribute to 1 if
using old 3DNOW insn rather than SSE/3DNOW_A.
(mmx_emms, mmx_femms): Clear modrm attribute.
2009-05-29 Martin Jambor <mjambor@suse.cz>
* tree-sra.c: New implementation of SRA.

117
gcc/config/i386/i386.c
View File

@ -19351,9 +19351,33 @@ memory_address_length (rtx addr)
len = 1;
}
/* Direct Addressing. */
/* Direct Addressing. In 64-bit mode mod 00 r/m 5
is not disp32, but disp32(%rip), so for disp32
SIB byte is needed, unless print_operand_address
optimizes it into disp32(%rip) or (%rip) is implied
by UNSPEC. */
else if (disp && !base && !index)
len = 4;
{
len = 4;
if (TARGET_64BIT)
{
rtx symbol = disp;
if (GET_CODE (disp) == CONST)
symbol = XEXP (disp, 0);
if (GET_CODE (symbol) == PLUS
&& CONST_INT_P (XEXP (symbol, 1)))
symbol = XEXP (symbol, 0);
if (GET_CODE (symbol) != LABEL_REF
&& (GET_CODE (symbol) != SYMBOL_REF
|| SYMBOL_REF_TLS_MODEL (symbol) != 0)
&& (GET_CODE (symbol) != UNSPEC
|| (XINT (symbol, 1) != UNSPEC_GOTPCREL
&& XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
len += 1;
}
}
else
{
@ -19368,7 +19392,7 @@ memory_address_length (rtx addr)
/* ebp always wants a displacement. Similarly r13. */
else if (REG_P (base)
&& (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
len = 1;
len = 1;
/* An index requires the two-byte modrm form.... */
if (index
@ -19380,6 +19404,16 @@ memory_address_length (rtx addr)
len += 1;
}
switch (parts.seg)
{
case SEG_FS:
case SEG_GS:
len += 1;
break;
default:
break;
}
return len;
}
@ -19394,30 +19428,50 @@ ix86_attr_length_immediate_default (rtx insn, int shortform)
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (CONSTANT_P (recog_data.operand[i]))
{
enum attr_mode mode = get_attr_mode (insn);
gcc_assert (!len);
if (shortform && satisfies_constraint_K (recog_data.operand[i]))
len = 1;
else
if (shortform && CONST_INT_P (recog_data.operand[i]))
{
switch (get_attr_mode (insn))
HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
switch (mode)
{
case MODE_QI:
len+=1;
break;
case MODE_HI:
len+=2;
break;
case MODE_SI:
len+=4;
break;
/* Immediates for DImode instructions are encoded as 32bit sign extended values. */
case MODE_DI:
len+=4;
break;
default:
fatal_insn ("unknown insn mode", insn);
case MODE_QI:
len = 1;
continue;
case MODE_HI:
ival = trunc_int_for_mode (ival, HImode);
break;
case MODE_SI:
ival = trunc_int_for_mode (ival, SImode);
break;
default:
break;
}
if (IN_RANGE (ival, -128, 127))
{
len = 1;
continue;
}
}
switch (mode)
{
case MODE_QI:
len = 1;
break;
case MODE_HI:
len = 2;
break;
case MODE_SI:
len = 4;
break;
/* Immediates for DImode instructions are encoded as 32bit sign extended values. */
case MODE_DI:
len = 4;
break;
default:
fatal_insn ("unknown insn mode", insn);
}
}
return len;
}
@ -19452,8 +19506,22 @@ ix86_attr_length_address_default (rtx insn)
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (MEM_P (recog_data.operand[i]))
{
constrain_operands_cached (reload_completed);
if (which_alternative != -1)
{
const char *constraints = recog_data.constraints[i];
int alt = which_alternative;
while (*constraints == '=' || *constraints == '+')
constraints++;
while (alt-- > 0)
while (*constraints++ != ',')
;
/* Skip ignored operands. */
if (*constraints == 'X')
continue;
}
return memory_address_length (XEXP (recog_data.operand[i], 0));
break;
}
return 0;
}
@ -19482,7 +19550,8 @@ ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
if (REG_P (recog_data.operand[i]))
{
/* REX.W bit uses 3 byte VEX prefix. */
if (GET_MODE (recog_data.operand[i]) == DImode)
if (GET_MODE (recog_data.operand[i]) == DImode
&& GENERAL_REG_P (recog_data.operand[i]))
return 3 + 1;
}
else

245
gcc/config/i386/i386.md
View File

@ -416,16 +416,23 @@
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
(if_then_else (ior (eq_attr "mode" "HI")
(and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI")))
(const_int 1)
(const_int 0)))
(cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
(const_int 0)
(eq_attr "mode" "HI")
(const_int 1)
(and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
(const_int 1)
]
(const_int 0)))
;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
(if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
(const_int 1)
(const_int 0)))
(cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
(const_int 0)
(and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
(const_int 1)
]
(const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
@ -440,7 +447,8 @@
(cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))
(const_int 0)
(and (eq_attr "mode" "DI")
(eq_attr "type" "!push,pop,call,callv,leave,ibr"))
(and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
(eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
(ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
@ -455,8 +463,17 @@
]
(const_int 0)))
;; There are also additional prefixes in SSSE3.
(define_attr "prefix_extra" "" (const_int 0))
;; There are also additional prefixes in 3DNOW, SSSE3 or SSE5.
;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
(define_attr "prefix_extra" ""
(cond [(eq_attr "type" "ssemuladd,sse4arg")
(const_int 2)
(eq_attr "type" "sseiadd1,ssecvt1")
(const_int 1)
]
(const_int 0)))
;; Prefix used: original, VEX or maybe VEX.
(define_attr "prefix" "orig,vex,maybe_vex"
@ -464,15 +481,16 @@
(const_string "vex")
(const_string "orig")))
;; There is a 8bit immediate for VEX.
(define_attr "prefix_vex_imm8" "" (const_int 0))
;; VEX W bit is used.
(define_attr "prefix_vex_w" "" (const_int 0))
;; The length of VEX prefix
;; Only instructions with 0f prefix can have 2 byte VEX prefix,
;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
;; still prefix_0f 1, with prefix_extra 1.
(define_attr "length_vex" ""
(if_then_else (eq_attr "prefix_0f" "1")
(if_then_else (and (eq_attr "prefix_0f" "1")
(eq_attr "prefix_extra" "0"))
(if_then_else (eq_attr "prefix_vex_w" "1")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))
@ -487,8 +505,9 @@
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
(ior (match_operand:SI 1 "register_operand" "")
(match_operand:HI 1 "register_operand" "")))
(and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
(ior (match_operand:SI 1 "register_operand" "")
(match_operand:HI 1 "register_operand" ""))))
(const_int 0)
(and (eq_attr "type" "push")
(not (match_operand 1 "memory_operand" "")))
@ -534,7 +553,7 @@
(and (eq_attr "prefix" "maybe_vex")
(ne (symbol_ref "TARGET_AVX") (const_int 0))))
(plus (attr "length_vex")
(plus (attr "prefix_vex_imm8")
(plus (attr "length_immediate")
(plus (attr "modrm")
(attr "length_address"))))]
(plus (plus (attr "modrm")
@ -1155,6 +1174,7 @@
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
@ -1169,6 +1189,7 @@
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_4"
@ -1516,7 +1537,7 @@
(unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
[(set_attr "length" "2")
[(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "SI")
(set_attr "unit" "i387")])
@ -1556,6 +1577,17 @@
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
(if_then_else (eq_attr "type" "ssecomi")
(const_string "0")
(const_string "*")))
(set (attr "prefix_data16")
(cond [(eq_attr "type" "fcmp")
(const_string "*")
(eq_attr "mode" "DF")
(const_string "1")
]
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
@ -1573,6 +1605,11 @@
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "DF")
(const_string "1")
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
@ -1610,6 +1647,17 @@
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
(if_then_else (eq_attr "type" "ssecomi")
(const_string "0")
(const_string "*")))
(set (attr "prefix_data16")
(cond [(eq_attr "type" "fcmp")
(const_string "*")
(eq_attr "mode" "DF")
(const_string "1")
]
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
@ -1627,6 +1675,11 @@
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "DF")
(const_string "1")
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
@ -1802,6 +1855,10 @@
(if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
(const_string "orig")
(const_string "maybe_vex")))
(set (attr "prefix_data16")
(if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
(const_string "1")
(const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
@ -2651,6 +2708,8 @@
(and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
(const_string "8")
(const_string "*")))
(set_attr "prefix_rex" "*,*,*,*,*,*,*,1,*,1,*,*,*,*,*,*,*,*,*")
(set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,1,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
(const_string "maybe_vex")
@ -3235,6 +3294,10 @@
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "V1DF")
(const_string "1")
(const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
@ -3369,6 +3432,10 @@
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "V1DF")
(const_string "1")
(const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
@ -3489,6 +3556,10 @@
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "V1DF")
(const_string "1")
(const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
@ -4194,7 +4265,7 @@
"TARGET_64BIT"
"@
{cltq|cdqe}
movs{lq|x}\t{%1,%0|%0, %1}"
movs{lq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")
(set_attr "prefix_0f" "0")
@ -4204,7 +4275,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
"movs{wq|x}\t{%1,%0|%0, %1}"
"movs{wq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
@ -4212,7 +4283,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"TARGET_64BIT"
"movs{bq|x}\t{%1,%0|%0, %1}"
"movs{bq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
@ -4300,7 +4371,7 @@
case 0:
return "{cwtl|cwde}";
default:
return "movs{wl|x}\t{%1,%0|%0, %1}";
return "movs{wl|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
@ -4327,7 +4398,7 @@
case 0:
return "{cwtl|cwde}";
default:
return "movs{wl|x}\t{%1,%k0|%k0, %1}";
return "movs{wl|x}\t{%1, %k0|%k0, %1}";
}
}
[(set_attr "type" "imovx")
@ -4353,7 +4424,7 @@
case 0:
return "{cbtw|cbw}";
default:
return "movs{bw|x}\t{%1,%0|%0, %1}";
return "movs{bw|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
@ -4373,7 +4444,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
""
"movs{bl|x}\t{%1,%0|%0, %1}"
"movs{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
@ -4382,7 +4453,7 @@
(zero_extend:DI
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
"TARGET_64BIT"
"movs{bl|x}\t{%1,%k0|%k0, %1}"
"movs{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
@ -4994,6 +5065,7 @@
"%vcvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex")
(set_attr "prefix_rex" "1")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
@ -5268,7 +5340,7 @@
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
[(set_attr "length" "2")
[(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")])
@ -5277,7 +5349,7 @@
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
[(set_attr "length" "2")
[(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
@ -6650,7 +6722,7 @@
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
@ -7121,7 +7193,7 @@
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
@ -7409,10 +7481,10 @@
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(set_attr "mode" "HI")])
(define_insn "*addhi_5"
@ -7808,6 +7880,7 @@
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_1_rex64"
@ -7844,6 +7917,7 @@
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_2"
@ -9308,6 +9382,7 @@
[(set_attr "type" "test")
(set_attr "mode" "QI")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "pent_pair" "np")])
(define_insn "*testqi_ext_1"
@ -9534,9 +9609,9 @@
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
return "movz{bq|x}\t{%1,%0|%0, %1}";
return "movz{bl|x}\t{%1, %k0|%k0, %1}";
else
return "movz{wq|x}\t{%1,%0|%0, %1}";
return "movz{wl|x}\t{%1, %k0|%k0, %1}";
}
default:
@ -9549,7 +9624,14 @@
}
[(set_attr "type" "alu,alu,alu,imovx")
(set_attr "length_immediate" "*,*,*,0")
(set_attr "mode" "SI,DI,DI,DI")])
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
(match_operand 1 "ext_QIreg_nomode_operand" "")))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI,DI,DI,SI")])
(define_insn "*anddi_2"
[(set (reg FLAGS_REG)
@ -9598,9 +9680,9 @@
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
return "movz{bl|x}\t{%1,%0|%0, %1}";
return "movz{bl|x}\t{%1, %0|%0, %1}";
else
return "movz{wl|x}\t{%1,%0|%0, %1}";
return "movz{wl|x}\t{%1, %0|%0, %1}";
}
default:
@ -9609,6 +9691,13 @@
}
}
[(set_attr "type" "alu,alu,imovx")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
(match_operand 1 "ext_QIreg_nomode_operand" "")))
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
@ -9717,6 +9806,12 @@
}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_nomode_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "HI,HI,SI")])
(define_insn "*andhi_2"
@ -9836,6 +9931,7 @@
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
;; Generated by peephole translating test to and. This shows up
@ -9864,6 +9960,7 @@
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1"
@ -10238,6 +10335,7 @@
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*iorqi_ext_1"
@ -10568,6 +10666,7 @@
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_ext_1"
@ -10686,6 +10785,7 @@
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
@ -10707,6 +10807,7 @@
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_expand "xorqi_cc_ext_1"
@ -11509,6 +11610,7 @@
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
@ -11522,6 +11624,7 @@
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*ashlti3_1"
@ -13361,6 +13464,7 @@
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_lshrti3"
@ -13374,6 +13478,7 @@
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*lshrti3_1"
@ -14446,7 +14551,8 @@
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"bts{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")])
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
@ -14457,7 +14563,8 @@
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btr{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")])
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
@ -14468,7 +14575,8 @@
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btc{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")])
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
;; Allow Nocona to avoid these instructions if a register is available.
@ -14580,7 +14688,8 @@
"TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"bt{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")])
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_insn "*btsi"
[(set (reg:CCC FLAGS_REG)
@ -14593,7 +14702,8 @@
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"bt{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")])
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
;; Store-flag instructions.
@ -14706,6 +14816,7 @@
"vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "prefix" "vex")
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "*sse_setcc<mode>"
@ -14716,6 +14827,7 @@
"SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "*sse5_setcc<mode>"
@ -14726,6 +14838,7 @@
"TARGET_SSE5"
"com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
@ -15821,7 +15934,8 @@
"TARGET_64BIT"
"lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
[(set_attr "type" "lea")
(set_attr "length" "6")])
(set_attr "length_address" "4")
(set_attr "mode" "DI")])
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
@ -15829,7 +15943,8 @@
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
(set_attr "length" "6")])
(set_attr "length_address" "4")
(set_attr "mode" "DI")])
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
@ -15839,7 +15954,9 @@
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
(set_attr "length" "11")])
(set_attr "length_immediate" "0")
(set_attr "length_address" "8")
(set_attr "mode" "DI")])
(define_expand "epilogue"
[(const_int 0)]
@ -15962,7 +16079,9 @@
(ctz:SI (match_dup 1)))]
""
"bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
@ -15988,7 +16107,9 @@
(ctz:DI (match_dup 1)))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_insn "ctzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@ -15996,7 +16117,9 @@
(clobber (reg:CC FLAGS_REG))]
""
"bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
(define_insn "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
@ -16004,7 +16127,9 @@
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_expand "clzsi2"
[(parallel
@ -16041,7 +16166,8 @@
(clobber (reg:CC FLAGS_REG))]
""
"bsr{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
(define_insn "popcount<mode>2"
@ -16225,7 +16351,8 @@
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsr{q}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_expand "clzhi2"
@ -16263,7 +16390,8 @@
(clobber (reg:CC FLAGS_REG))]
""
"bsr{w}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
(define_expand "paritydi2"
@ -19363,6 +19491,7 @@
"TARGET_USE_FANCY_MATH_387"
"fxam\n\tfnstsw\t%0"
[(set_attr "type" "multi")
(set_attr "length" "4")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")])
@ -22316,6 +22445,7 @@
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
(set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_sse_rex"
@ -22335,6 +22465,7 @@
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
(set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
@ -22349,6 +22480,7 @@
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
(set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow_rex"
@ -22363,6 +22495,7 @@
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
(set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
@ -22520,6 +22653,14 @@
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
(set (attr "prefix_data16")
(if_then_else (match_operand:HI 2 "" "")
(const_string "1")
(const_string "*")))
(set (attr "prefix_rex")
(if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(define_insn "sse4_2_crc32di"

63
gcc/config/i386/mmx.md
View File

@ -1,5 +1,5 @@
;; GCC machine description for MMX and 3dNOW! instructions
;; Copyright (C) 2005, 2007, 2008
;; Copyright (C) 2005, 2007, 2008, 2009
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
@ -85,6 +85,12 @@
%vmovq\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
(set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,1,1,1")
(set (attr "prefix_rex")
(if_then_else (eq_attr "alternative" "8,9")
(symbol_ref "x86_extended_reg_mentioned_p (insn)")
(const_string "*")))
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "7,8,9,10,11")
(const_string "maybe_vex")
@ -111,6 +117,7 @@
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "5,6,7")
(const_string "vex")
@ -141,6 +148,8 @@
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,1,1,*,1,*,*,*,*,*,*,*")
(set_attr "prefix_data16" "*,*,*,*,*,*,*,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
(define_expand "movv2sf"
@ -175,6 +184,8 @@
vmovq\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
(set_attr "length_vex" "*,*,*,*,*,*,*,*,*,*,*,4,4")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "7,8,9,10,11,12")
(const_string "vex")
@ -204,6 +215,7 @@
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
(define_insn "*movv2sf_internal_avx"
@ -227,6 +239,7 @@
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "5,6,7,8")
(const_string "vex")
@ -254,6 +267,7 @@
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
;; %%% This multiword shite has got to go.
@ -313,6 +327,7 @@
"TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
"pfadd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_expand "mmx_subv2sf3"
@ -338,6 +353,7 @@
pfsub\t{%2, %0|%0, %2}
pfsubr\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_expand "mmx_mulv2sf3"
@ -354,6 +370,7 @@
"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
"pfmul\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxmul")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
@ -381,6 +398,7 @@
&& ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "*mmx_<code>v2sf3"
@ -391,6 +409,7 @@
"TARGET_3DNOW"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpv2sf2"
@ -400,6 +419,7 @@
"TARGET_3DNOW"
"pfrcp\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpit1v2sf3"
@ -410,6 +430,7 @@
"TARGET_3DNOW"
"pfrcpit1\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpit2v2sf3"
@ -420,6 +441,7 @@
"TARGET_3DNOW"
"pfrcpit2\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rsqrtv2sf2"
@ -429,6 +451,7 @@
"TARGET_3DNOW"
"pfrsqrt\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rsqit1v2sf3"
@ -439,6 +462,7 @@
"TARGET_3DNOW"
"pfrsqit1\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_haddv2sf3"
@ -457,6 +481,7 @@
"TARGET_3DNOW"
"pfacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_hsubv2sf3"
@ -475,6 +500,7 @@
"TARGET_3DNOW_A"
"pfnacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_addsubv2sf3"
@ -488,6 +514,7 @@
"TARGET_3DNOW_A"
"pfpnacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@ -510,6 +537,7 @@
"TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
"pfcmpeq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_gtv2sf3"
@ -519,6 +547,7 @@
"TARGET_3DNOW"
"pfcmpgt\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_gev2sf3"
@ -528,6 +557,7 @@
"TARGET_3DNOW"
"pfcmpge\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@ -542,6 +572,7 @@
"TARGET_3DNOW"
"pf2id\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_pf2iw"
@ -553,6 +584,7 @@
"TARGET_3DNOW_A"
"pf2iw\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_pi2fw"
@ -564,6 +596,7 @@
"TARGET_3DNOW_A"
"pi2fw\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_floatv2si2"
@ -572,6 +605,7 @@
"TARGET_3DNOW"
"pi2fd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@ -587,6 +621,7 @@
"TARGET_3DNOW_A"
"pswapd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "*vec_dupv2sf"
@ -887,6 +922,7 @@
"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
"pmulhrw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxmul")
(set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_expand "sse2_umulv1siv1di3"
@ -965,6 +1001,10 @@
"TARGET_MMX"
"psra<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
(set_attr "mode" "DI")])
(define_insn "mmx_lshr<mode>3"
@ -975,6 +1015,10 @@
"TARGET_MMX"
"psrl<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
(set_attr "mode" "DI")])
(define_insn "mmx_ashl<mode>3"
@ -985,6 +1029,10 @@
"TARGET_MMX"
"psll<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
(set_attr "mode" "DI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@ -1205,6 +1253,7 @@
return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
}
[(set_attr "type" "mmxcvt")
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "mmx_pextrw"
@ -1216,6 +1265,7 @@
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "mmxcvt")
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_expand "mmx_pshufw"
@ -1253,6 +1303,7 @@
return "pshufw\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "mmxcvt")
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "mmx_pswapdv2si2"
@ -1263,6 +1314,7 @@
"TARGET_3DNOW_A"
"pswapd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
(set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "*vec_dupv4hi"
@ -1273,6 +1325,7 @@
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "type" "mmxcvt")
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "*vec_dupv2si"
@ -1345,6 +1398,7 @@
#
#"
[(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
(set_attr "length_immediate" "*,*,1,*,*,*,*")
(set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
(define_split
@ -1492,6 +1546,11 @@
return "pavgusb\t{%2, %0|%0, %2}";
}
[(set_attr "type" "mmxshft")
(set (attr "prefix_extra")
(if_then_else
(eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
(define_expand "mmx_uavgv4hi3"
@ -1602,6 +1661,7 @@
"TARGET_MMX"
"emms"
[(set_attr "type" "mmx")
(set_attr "modrm" "0")
(set_attr "memory" "unknown")])
(define_insn "mmx_femms"
@ -1625,4 +1685,5 @@
"TARGET_3DNOW"
"femms"
[(set_attr "type" "mmx")
(set_attr "modrm" "0")
(set_attr "memory" "none")])

11
gcc/config/i386/predicates.md
View File

@ -84,6 +84,12 @@
&& GET_MODE (op) == QImode
&& REGNO (op) > BX_REG")))
;; Similarly, but don't check mode of the operand.
(define_predicate "ext_QIreg_nomode_operand"
(and (match_code "reg")
(match_test "TARGET_64BIT
&& REGNO (op) > BX_REG")))
;; Return true if op is not xmm0 register.
(define_predicate "reg_not_xmm0_operand"
(and (match_operand 0 "register_operand")
@ -587,11 +593,6 @@
(and (match_code "const_int")
(match_test "INTVAL (op) == 128")))
;; Match exactly -128.
(define_predicate "constm128_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) == -128")))
;; Match 2, 4, or 8. Used for leal multiplicands.
(define_predicate "const248_operand"
(match_code "const_int")

322
gcc/config/i386/sse.md
View File

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