arm: Replace arm_builtin_vectorized_function [PR106253]
This patch extends the fix for PR106253 to AArch32. As with AArch64,
we were using ACLE intrinsics to vectorise scalar built-ins, even
though the two sometimes have different ECF_* flags. (That in turn
is because the ACLE intrinsics should follow the instruction semantics
as closely as possible, whereas the scalar built-ins follow language
specs.)
The patch also removes the copysignf built-in, which only existed
for this purpose and wasn't a “real” arm_neon.h built-in.
Doing this also has the side-effect of enabling vectorisation of
rint and roundeven. Logically that should be a separate patch,
but making it one would have meant adding a new int iterator
for the original set of instructions and then removing it again
when including new functions.
I've restricted the bswap tests to little-endian because we end
up with excessive spilling on big-endian. E.g.:
sub sp, sp, #8
vstr d1, [sp]
vldr d16, [sp]
vrev16.8 d16, d16
vstr d16, [sp]
vldr d0, [sp]
add sp, sp, #8
@ sp needed
bx lr
Similarly, the copysign tests require little-endian because on
big-endian we unnecessarily load the constant from the constant pool:
vldr.32 s15, .L3
vdup.32 d0, d7[1]
vbsl d0, d2, d1
bx lr
.L3:
.word -2147483648
gcc/
PR target/106253
* config/arm/arm-builtins.cc (arm_builtin_vectorized_function):
Delete.
* config/arm/arm-protos.h (arm_builtin_vectorized_function): Delete.
* config/arm/arm.cc (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION):
Delete.
* config/arm/arm_neon_builtins.def (copysignf): Delete.
* config/arm/iterators.md (nvrint_pattern): New attribute.
* config/arm/neon.md (<NEON_VRINT:nvrint_pattern><VCVTF:mode>2):
New pattern.
(l<NEON_VCVT:nvrint_pattern><su_optab><VCVTF:mode><v_cmp_result>2):
Likewise.
(neon_copysignf<mode>): Rename to...
(copysign<mode>3): ...this.
gcc/testsuite/
PR target/106253
* gcc.target/arm/vect_unary_1.c: New test.
* gcc.target/arm/vect_binary_1.c: Likewise.
This commit is contained in:
Richard Sandiford
parent
9c8349ee1a
commit
7313381d2c
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@ -4026,129 +4026,6 @@ arm_expand_builtin (tree exp,
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return NULL_RTX;
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}
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tree
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arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)
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{
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machine_mode in_mode, out_mode;
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int in_n, out_n;
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bool out_unsigned_p = TYPE_UNSIGNED (type_out);
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/* Can't provide any vectorized builtins when we can't use NEON. */
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if (!TARGET_NEON)
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return NULL_TREE;
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if (TREE_CODE (type_out) != VECTOR_TYPE
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|| TREE_CODE (type_in) != VECTOR_TYPE)
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return NULL_TREE;
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out_mode = TYPE_MODE (TREE_TYPE (type_out));
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out_n = TYPE_VECTOR_SUBPARTS (type_out);
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in_mode = TYPE_MODE (TREE_TYPE (type_in));
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in_n = TYPE_VECTOR_SUBPARTS (type_in);
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/* ARM_CHECK_BUILTIN_MODE and ARM_FIND_VRINT_VARIANT are used to find the
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decl of the vectorized builtin for the appropriate vector mode.
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NULL_TREE is returned if no such builtin is available. */
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#undef ARM_CHECK_BUILTIN_MODE
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#define ARM_CHECK_BUILTIN_MODE(C) \
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(TARGET_VFP5 \
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&& flag_unsafe_math_optimizations \
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&& ARM_CHECK_BUILTIN_MODE_1 (C))
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#undef ARM_CHECK_BUILTIN_MODE_1
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#define ARM_CHECK_BUILTIN_MODE_1(C) \
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(out_mode == SFmode && out_n == C \
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&& in_mode == SFmode && in_n == C)
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#undef ARM_FIND_VRINT_VARIANT
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#define ARM_FIND_VRINT_VARIANT(N) \
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(ARM_CHECK_BUILTIN_MODE (2) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sf, false) \
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: (ARM_CHECK_BUILTIN_MODE (4) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sf, false) \
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: NULL_TREE))
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switch (fn)
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{
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CASE_CFN_FLOOR:
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return ARM_FIND_VRINT_VARIANT (vrintm);
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CASE_CFN_CEIL:
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return ARM_FIND_VRINT_VARIANT (vrintp);
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CASE_CFN_TRUNC:
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return ARM_FIND_VRINT_VARIANT (vrintz);
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CASE_CFN_ROUND:
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return ARM_FIND_VRINT_VARIANT (vrinta);
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#undef ARM_CHECK_BUILTIN_MODE_1
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#define ARM_CHECK_BUILTIN_MODE_1(C) \
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(out_mode == SImode && out_n == C \
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&& in_mode == SFmode && in_n == C)
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#define ARM_FIND_VCVT_VARIANT(N) \
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(ARM_CHECK_BUILTIN_MODE (2) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sfv2si, false) \
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: (ARM_CHECK_BUILTIN_MODE (4) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sfv4si, false) \
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: NULL_TREE))
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#define ARM_FIND_VCVTU_VARIANT(N) \
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(ARM_CHECK_BUILTIN_MODE (2) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##uv2sfv2si, false) \
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: (ARM_CHECK_BUILTIN_MODE (4) \
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? arm_builtin_decl(ARM_BUILTIN_NEON_##N##uv4sfv4si, false) \
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: NULL_TREE))
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CASE_CFN_LROUND:
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return (out_unsigned_p
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? ARM_FIND_VCVTU_VARIANT (vcvta)
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: ARM_FIND_VCVT_VARIANT (vcvta));
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CASE_CFN_LCEIL:
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return (out_unsigned_p
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? ARM_FIND_VCVTU_VARIANT (vcvtp)
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: ARM_FIND_VCVT_VARIANT (vcvtp));
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CASE_CFN_LFLOOR:
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return (out_unsigned_p
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? ARM_FIND_VCVTU_VARIANT (vcvtm)
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: ARM_FIND_VCVT_VARIANT (vcvtm));
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#undef ARM_CHECK_BUILTIN_MODE
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#define ARM_CHECK_BUILTIN_MODE(C, N) \
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(out_mode == N##mode && out_n == C \
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&& in_mode == N##mode && in_n == C)
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case CFN_BUILT_IN_BSWAP16:
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if (ARM_CHECK_BUILTIN_MODE (4, HI))
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return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv4hi, false);
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else if (ARM_CHECK_BUILTIN_MODE (8, HI))
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return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv8hi, false);
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else
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return NULL_TREE;
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case CFN_BUILT_IN_BSWAP32:
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if (ARM_CHECK_BUILTIN_MODE (2, SI))
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return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv2si, false);
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else if (ARM_CHECK_BUILTIN_MODE (4, SI))
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return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv4si, false);
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else
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return NULL_TREE;
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case CFN_BUILT_IN_BSWAP64:
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if (ARM_CHECK_BUILTIN_MODE (2, DI))
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return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv2di, false);
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else
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return NULL_TREE;
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CASE_CFN_COPYSIGN:
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if (ARM_CHECK_BUILTIN_MODE (2, SF))
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return arm_builtin_decl (ARM_BUILTIN_NEON_copysignfv2sf, false);
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else if (ARM_CHECK_BUILTIN_MODE (4, SF))
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return arm_builtin_decl (ARM_BUILTIN_NEON_copysignfv4sf, false);
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else
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return NULL_TREE;
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default:
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return NULL_TREE;
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}
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return NULL_TREE;
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}
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#undef ARM_FIND_VCVT_VARIANT
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#undef ARM_FIND_VCVTU_VARIANT
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#undef ARM_CHECK_BUILTIN_MODE
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#undef ARM_FIND_VRINT_VARIANT
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void
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arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
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{
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@ -103,7 +103,6 @@ extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
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rtx (*) (rtx, rtx, rtx));
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extern rtx mve_bool_vec_to_const (rtx const_vec);
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extern rtx neon_make_constant (rtx, bool generate = true);
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extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
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extern void neon_expand_vector_init (rtx, rtx);
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extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
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extern void arm_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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@ -739,10 +739,6 @@ static const struct attribute_spec arm_attribute_table[] =
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#undef TARGET_VECTORIZE_BUILTINS
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#define TARGET_VECTORIZE_BUILTINS
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#undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
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#define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
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arm_builtin_vectorized_function
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#undef TARGET_VECTOR_ALIGNMENT
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#define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
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@ -264,7 +264,6 @@ VAR1 (UNOP, vcvtv4hf, v4sf)
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VAR10 (TERNOP, vbsl,
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v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
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VAR2 (TERNOP, vbsl, v8hf, v4hf)
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VAR2 (UNOP, copysignf, v2sf, v4sf)
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VAR2 (UNOP, vrintn, v2sf, v4sf)
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VAR2 (UNOP, vrinta, v2sf, v4sf)
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VAR2 (UNOP, vrintp, v2sf, v4sf)
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@ -1150,6 +1150,13 @@
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(UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
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(UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
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(define_int_attr nvrint_pattern [(UNSPEC_NVRINTZ "btrunc")
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(UNSPEC_NVRINTP "ceil")
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(UNSPEC_NVRINTA "round")
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(UNSPEC_NVRINTM "floor")
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(UNSPEC_NVRINTX "rint")
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(UNSPEC_NVRINTN "roundeven")])
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(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
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(UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
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(UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
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@ -635,6 +635,13 @@
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[(set_attr "type" "neon_fp_mla_s<q>")]
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)
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(define_expand "<NEON_VRINT:nvrint_pattern><VCVTF:mode>2"
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[(set (match_operand:VCVTF 0 "s_register_operand")
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(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand")]
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NEON_VRINT))]
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"TARGET_NEON && TARGET_VFP5 && flag_unsafe_math_optimizations"
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)
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(define_insn "neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>"
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[(set (match_operand:VCVTF 0 "s_register_operand" "=w")
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(unspec:VCVTF [(match_operand:VCVTF 1
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@ -645,6 +652,14 @@
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[(set_attr "type" "neon_fp_round_<V_elem_ch><q>")]
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)
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(define_expand "l<NEON_VCVT:nvrint_pattern><su_optab><VCVTF:mode><v_cmp_result>2"
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[(set (match_operand:<V_cmp_result> 0 "register_operand")
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(FIXUORS:<V_cmp_result>
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(unspec:VCVTF [(match_operand:VCVTF 1 "register_operand")]
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NEON_VCVT)))]
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"TARGET_NEON && TARGET_VFP5 && flag_unsafe_math_optimizations"
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)
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(define_insn "neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode><v_cmp_result>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
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(FIXUORS:<V_cmp_result> (unspec:VCVTF
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@ -3059,7 +3074,7 @@
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"TARGET_I8MM"
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)
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(define_expand "neon_copysignf<mode>"
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(define_expand "copysign<mode>3"
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[(match_operand:VCVTF 0 "register_operand")
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(match_operand:VCVTF 1 "register_operand")
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(match_operand:VCVTF 2 "register_operand")]
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@ -0,0 +1,50 @@
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/* { dg-do compile { target { arm*-*-* } } } */
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/* { dg-require-effective-target arm_hard_ok } */
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/* { dg-require-effective-target arm_v8_neon_ok } */
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/* { dg-add-options arm_v8_neon } */
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/* { dg-additional-options "-O3 -mfloat-abi=hard" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#include <stdint.h>
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#define TEST2(OUT, NAME, IN) \
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OUT __attribute__((vector_size(sizeof(OUT) * 2))) \
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test2_##OUT##_##NAME##_##IN (float dummy, \
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IN __attribute__((vector_size(sizeof(IN) * 2))) y, \
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IN __attribute__((vector_size(sizeof(IN) * 2))) z) \
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{ \
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OUT __attribute__((vector_size(sizeof(OUT) * 2))) x; \
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x[0] = __builtin_##NAME (y[0], z[0]); \
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x[1] = __builtin_##NAME (y[1], z[1]); \
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return x; \
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}
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#define TEST4(OUT, NAME, IN) \
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OUT __attribute__((vector_size(sizeof(OUT) * 4))) \
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test4_##OUT##_##NAME##_##IN (float dummy, \
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IN __attribute__((vector_size(sizeof(OUT) * 4))) y, \
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IN __attribute__((vector_size(sizeof(OUT) * 4))) z) \
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{ \
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OUT __attribute__((vector_size(sizeof(OUT) * 4))) x; \
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x[0] = __builtin_##NAME (y[0], z[0]); \
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x[1] = __builtin_##NAME (y[1], z[1]); \
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x[2] = __builtin_##NAME (y[2], z[2]); \
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x[3] = __builtin_##NAME (y[3], z[3]); \
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return x; \
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}
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/*
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** test2_float_copysignf_float: { target arm_little_endian }
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** vmov.i32 d0, #(0x80000000|2147483648)(\s+.*)
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** vbsl d0, d2, d1
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** bx lr
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*/
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TEST2 (float, copysignf, float)
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/*
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** test4_float_copysignf_float: { target arm_little_endian }
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** vmov.i32 q0, #(0x80000000|2147483648)(\s+.*)
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** vbsl q0, q2, q1
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** bx lr
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*/
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TEST4 (float, copysignf, float)
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@ -0,0 +1,224 @@
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/* { dg-do compile { target { arm*-*-* } } } */
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/* { dg-require-effective-target arm_hard_ok } */
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/* { dg-require-effective-target arm_v8_neon_ok } */
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/* { dg-add-options arm_v8_neon } */
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/* { dg-additional-options "-Ofast -mfloat-abi=hard" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#include <stdint.h>
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#define TEST2(OUT, NAME, IN) \
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OUT __attribute__((vector_size(sizeof(OUT) * 2))) \
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test2_##OUT##_##NAME##_##IN (float dummy, \
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IN __attribute__((vector_size(sizeof(IN) * 2))) y) \
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{ \
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OUT __attribute__((vector_size(sizeof(OUT) * 2))) x; \
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x[0] = __builtin_##NAME (y[0]); \
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x[1] = __builtin_##NAME (y[1]); \
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return x; \
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}
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#define TEST4(OUT, NAME, IN) \
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OUT __attribute__((vector_size(sizeof(OUT) * 4))) \
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test4_##OUT##_##NAME##_##IN (float dummy, \
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IN __attribute__((vector_size(sizeof(OUT) * 4))) y) \
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{ \
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OUT __attribute__((vector_size(sizeof(OUT) * 4))) x; \
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x[0] = __builtin_##NAME (y[0]); \
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x[1] = __builtin_##NAME (y[1]); \
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x[2] = __builtin_##NAME (y[2]); \
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x[3] = __builtin_##NAME (y[3]); \
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return x; \
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}
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#define TEST8(OUT, NAME, IN) \
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OUT __attribute__((vector_size(sizeof(OUT) * 8))) \
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test8_##OUT##_##NAME##_##IN (float dummy, \
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IN __attribute__((vector_size(sizeof(OUT) * 8))) y) \
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{ \
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OUT __attribute__((vector_size(sizeof(OUT) * 8))) x; \
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x[0] = __builtin_##NAME (y[0]); \
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x[1] = __builtin_##NAME (y[1]); \
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x[2] = __builtin_##NAME (y[2]); \
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x[3] = __builtin_##NAME (y[3]); \
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x[4] = __builtin_##NAME (y[4]); \
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x[5] = __builtin_##NAME (y[5]); \
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x[6] = __builtin_##NAME (y[6]); \
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x[7] = __builtin_##NAME (y[7]); \
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return x; \
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}
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/*
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** test2_float_truncf_float:
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** vrintz.f32 d0, d1
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** bx lr
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*/
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TEST2 (float, truncf, float)
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/*
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** test4_float_truncf_float:
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** vrintz.f32 q0, q1
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** bx lr
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*/
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TEST4 (float, truncf, float)
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/*
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** test2_float_roundf_float:
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** vrinta.f32 d0, d1
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** bx lr
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*/
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TEST2 (float, roundf, float)
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/*
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** test4_float_roundf_float:
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** vrinta.f32 q0, q1
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** bx lr
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*/
|
||||
TEST4 (float, roundf, float)
|
||||
|
||||
/*
|
||||
** test2_float_floorf_float:
|
||||
** vrintm.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (float, floorf, float)
|
||||
|
||||
/*
|
||||
** test4_float_floorf_float:
|
||||
** vrintm.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (float, floorf, float)
|
||||
|
||||
/*
|
||||
** test2_float_ceilf_float:
|
||||
** vrintp.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (float, ceilf, float)
|
||||
|
||||
/*
|
||||
** test4_float_ceilf_float:
|
||||
** vrintp.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (float, ceilf, float)
|
||||
|
||||
/*
|
||||
** test2_float_rintf_float:
|
||||
** vrintx.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (float, rintf, float)
|
||||
|
||||
/*
|
||||
** test4_float_rintf_float:
|
||||
** vrintx.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (float, rintf, float)
|
||||
|
||||
/*
|
||||
** test2_float_roundevenf_float:
|
||||
** vrintn.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (float, roundevenf, float)
|
||||
|
||||
/*
|
||||
** test4_float_roundevenf_float:
|
||||
** vrintn.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (float, roundevenf, float)
|
||||
|
||||
/*
|
||||
** test2_int_roundf_float:
|
||||
** vcvta.s32.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int, roundf, float)
|
||||
|
||||
/*
|
||||
** test4_int_roundf_float:
|
||||
** vcvta.s32.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int, roundf, float)
|
||||
|
||||
/*
|
||||
** test2_int_floorf_float:
|
||||
** vcvtm.s32.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int, floorf, float)
|
||||
|
||||
/*
|
||||
** test4_int_floorf_float:
|
||||
** vcvtm.s32.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int, floorf, float)
|
||||
|
||||
/*
|
||||
** test2_int_ceilf_float:
|
||||
** vcvtp.s32.f32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int, ceilf, float)
|
||||
|
||||
/*
|
||||
** test4_int_ceilf_float:
|
||||
** vcvtp.s32.f32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int, ceilf, float)
|
||||
|
||||
/*
|
||||
** test2_int_clz_int:
|
||||
** vclz.i32 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int, clz, int)
|
||||
|
||||
/*
|
||||
** test4_int_clz_int:
|
||||
** vclz.i32 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int, clz, int)
|
||||
|
||||
/*
|
||||
** test4_int16_t_bswap16_int16_t: { target arm_little_endian }
|
||||
** vrev16.8 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int16_t, bswap16, int16_t)
|
||||
|
||||
/*
|
||||
** test8_int16_t_bswap16_int16_t: { target arm_little_endian }
|
||||
** vrev16.8 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST8 (int16_t, bswap16, int16_t)
|
||||
|
||||
/*
|
||||
** test2_int_bswap32_int: { target arm_little_endian }
|
||||
** vrev32.8 d0, d1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int, bswap32, int)
|
||||
|
||||
/*
|
||||
** test4_int_bswap32_int: { target arm_little_endian }
|
||||
** vrev32.8 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST4 (int, bswap32, int)
|
||||
|
||||
/*
|
||||
** test2_int64_t_bswap64_int64_t: { target arm_little_endian }
|
||||
** vrev64.8 q0, q1
|
||||
** bx lr
|
||||
*/
|
||||
TEST2 (int64_t, bswap64, int64_t)
|
||||
Loading…
Reference in New Issue