From 73380abd6b2783215c7950a2ade5e3f4b271e2bc Mon Sep 17 00:00:00 2001 From: Stam Markianos-Wright Date: Mon, 27 Jan 2020 18:21:46 +0000 Subject: [PATCH] Hi all, This was committed following offline approval by Kyryl. One minor intended optimisation introduced by : https://gcc.gnu.org/ml/gcc-patches/2020-01/msg01237.html was to set a preference for both __fp16 types and __bf16 types to be loaded/stored directly into/from the FP/NEON registers (if they are available and if the vld1.16 is compatible), rather than be passed through the regular r-registers. This would convert many observed instances of: ** ldrh r3, [r3] @ __fp16 ** vmov.f16 s15, r3 @ __fp16 Into a single: ** vld1.16 {d7[2]}, [r3] This resulted in a regression of a dg-scan-assembler in a __fp16 test. This patch updates the test to the same testing standard used by the BFloat tests (use check-function-bodies to explicitly check for correct assembler generated by each function) and updates it for the latest optimisation. Cheers, Stam gcc/testsuite/ChangeLog: 2020-01-27 Stam Markianos-Wright * gcc.target/arm/armv8_2-fp16-move-1.c: Update following load/store optimisation. --- gcc/testsuite/ChangeLog | 5 ++ .../gcc.target/arm/armv8_2-fp16-move-1.c | 46 +++++++++++++++++-- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b4f298a7ea0..f81caf56ef6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-01-27 Stam Markianos-Wright + + * gcc.target/arm/armv8_2-fp16-move-1.c: Update following load/store + optimisation. + 2020-01-27 David Malcolm PR analyzer/93349 diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c index 2321dd38cc6..009bb8d1575 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c @@ -3,39 +3,78 @@ /* { dg-options "-O2" } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ /* { dg-additional-options "-mfloat-abi=hard" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* +**test_load_1: +** ... +** vld1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ __fp16 test_load_1 (__fp16* a) { return *a; } +/* +**test_load_2: +** ... +** vld1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ __fp16 test_load_2 (__fp16* a, int i) { return a[i]; } - +/* +**test_store_1: +** ... +** vst1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ void test_store_1 (__fp16* a, __fp16 b) { *a = b; } +/* +**test_store_2: +** ... +** vst1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ void test_store_2 (__fp16* a, int i, __fp16 b) { a[i] = b; } - +/* +**test_load_store_1: +** ... +** vld1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +** vst1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ __fp16 test_load_store_1 (__fp16* a, int i, __fp16* b) { a[i] = b[i]; } +/* +**test_load_store_2: +** ... +** vld1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +** vst1.16 {d[0-9]+\[[0-9]+\]}, \[r[0-9]+\] +** ... +*/ __fp16 test_load_store_2 (__fp16* a, int i, __fp16* b) { @@ -43,9 +82,6 @@ test_load_store_2 (__fp16* a, int i, __fp16* b) return a[i]; } -/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ -/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ - __fp16 test_select_1 (int sel, __fp16 a, __fp16 b) {