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mips.md (define_attr accum_in): New instruction attribute. 

* config/mips/mips.md (define_attr accum_in): New instruction attribute.
	Set it for imadd and fmadd patterns.
	* config/mips/mips.c (mips_linked_madd_p): Use accum_in to extract
	accumulator register.

From-SVN: r190406
This commit is contained in:
Maxim Kuvyrkov 2012-08-15 05:56:08 +00:00
parent f5cc3cbbcf
commit 73590b4f3a
2 changed files with 37 additions and 13 deletions
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25
gcc/config/mips/mips.c
View File

@ -12372,25 +12372,24 @@ mips_output_division (const char *division, rtx *operands)
bool
mips_linked_madd_p (rtx out_insn, rtx in_insn)
{
rtx x;
enum attr_accum_in accum_in;
int accum_in_opnum;
rtx accum_in_op;
x = single_set (in_insn);
if (x == 0)
if (recog_memoized (in_insn) < 0)
return false;
x = SET_SRC (x);
accum_in = get_attr_accum_in (in_insn);
if (accum_in == ACCUM_IN_NONE)
return false;
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == MULT
&& reg_set_p (XEXP (x, 1), out_insn))
return true;
accum_in_opnum = accum_in - ACCUM_IN_0;
if (GET_CODE (x) == MINUS
&& GET_CODE (XEXP (x, 1)) == MULT
&& reg_set_p (XEXP (x, 0), out_insn))
return true;
extract_insn (in_insn);
gcc_assert (accum_in_opnum < recog_data.n_operands);
accum_in_op = recog_data.operand[accum_in_opnum];
return false;
return reg_set_p (accum_in_op, out_insn);
}
/* True if the dependency between OUT_INSN and IN_INSN is on the store

25
gcc/config/mips/mips.md
View File

@ -274,6 +274,8 @@
;; "11" specifies MEMMODEL_ACQUIRE.
(define_attr "sync_memmodel" "" (const_int 10))
;; Accumulator operand for madd patterns.
(define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
;; Classification of each insn.
;; branch conditional branch
@ -1602,6 +1604,7 @@
madd\t%1,%2
#"
[(set_attr "type" "imadd")
(set_attr "accum_in" "3")
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
@ -1620,6 +1623,7 @@
madd\t%0,%1,%2
#"
[(set_attr "type" "imadd")
(set_attr "accum_in" "3")
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
@ -1658,6 +1662,7 @@
return "%[macc\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "accum_in" "3")
(set_attr "mode" "SI")])
(define_insn "*msac"
@ -1676,6 +1681,7 @@
return "msac\t$0,%2,%3";
}
[(set_attr "type" "imadd")
(set_attr "accum_in" "1")
(set_attr "mode" "SI")])
;; An msac-like instruction implemented using negation and a macc.
@ -1699,6 +1705,7 @@
(clobber (match_dup 4))])]
""
[(set_attr "type" "imadd")
(set_attr "accum_in" "1")
(set_attr "length" "8")])
;; Patterns generated by the define_peephole2 below.
@ -1715,6 +1722,7 @@
"ISA_HAS_MACC && reload_completed"
"macc\t%3,%1,%2"
[(set_attr "type" "imadd")
(set_attr "accum_in" "0")
(set_attr "mode" "SI")])
(define_insn "*msac2"
@ -1729,6 +1737,7 @@
"ISA_HAS_MSAC && reload_completed"
"msac\t%3,%1,%2"
[(set_attr "type" "imadd")
(set_attr "accum_in" "0")
(set_attr "mode" "SI")])
;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
@ -1831,6 +1840,7 @@
msub\t%2,%3
#"
[(set_attr "type" "imadd")
(set_attr "accum_in" "1")
(set_attr "mode" "SI")
(set_attr "length" "4,8")])
@ -2040,6 +2050,7 @@
return "msac<u>\t$0,%1,%2";
}
[(set_attr "type" "imadd")
(set_attr "accum_in" "3")
(set_attr "mode" "SI")])
;; _highpart patterns
@ -2260,6 +2271,7 @@
"TARGET_MAD"
"mad\t%1,%2"
[(set_attr "type" "imadd")
(set_attr "accum_in" "0")
(set_attr "mode" "SI")])
;; See the comment above <u>msubsidi4 for the relationship between
@ -2284,6 +2296,7 @@
return "%[macc<u>\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "accum_in" "3")
(set_attr "mode" "SI")])
;; Floating point multiply accumulate instructions.
@ -2296,6 +2309,7 @@
"ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"madd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*madd3<mode>"
@ -2306,6 +2320,7 @@
"ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
"madd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*msub4<mode>"
@ -2316,6 +2331,7 @@
"ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"msub.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*msub3<mode>"
@ -2326,6 +2342,7 @@
"ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
"msub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmadd4<mode>"
@ -2340,6 +2357,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmadd3<mode>"
@ -2354,6 +2372,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmadd4<mode>_fastmath"
@ -2368,6 +2387,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmadd3<mode>_fastmath"
@ -2382,6 +2402,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "3")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmsub4<mode>"
@ -2396,6 +2417,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "1")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmsub3<mode>"
@ -2410,6 +2432,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "1")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmsub4<mode>_fastmath"
@ -2424,6 +2447,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "1")
(set_attr "mode" "<UNITMODE>")])
(define_insn "*nmsub3<mode>_fastmath"
@ -2438,6 +2462,7 @@
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "accum_in" "1")
(set_attr "mode" "<UNITMODE>")])
;;