testsuite: aarch64: Add tests for vpaddq intrinsics
Add tests for vpaddq_* Neon intrinsics. Since these intrinsics are only supported for AArch64, these tests are restricted to only run on AArch64 targets. gcc/testsuite/ChangeLog: 2021-02-09 Jonathan Wright <jonathan.wright@arm.com> * gcc.target/aarch64/advsimd-intrinsics/vpXXXq.inc: New test template. * gcc.target/aarch64/advsimd-intrinsics/vpaddq.c: New test.
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Jonathan Wright
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#define FNNAME1(NAME) exec_ ## NAME
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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/* Basic test: y=OP(x), then store the result. */
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#define TEST_VPXXXQ1(INSN, T1, T2, W, N) \
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VECT_VAR(vector_res, T1, W, N) = \
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INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
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VECT_VAR(vector, T1, W, N)); \
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vst1q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N))
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#define TEST_VPXXXQ(INSN, T1, T2, W, N) \
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TEST_VPXXXQ1(INSN, T1, T2, W, N) \
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DECL_VARIABLE(vector, int, 8, 16);
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DECL_VARIABLE(vector, int, 16, 8);
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DECL_VARIABLE(vector, int, 32, 4);
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DECL_VARIABLE(vector, int, 64, 2);
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DECL_VARIABLE(vector, uint, 8, 16);
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DECL_VARIABLE(vector, uint, 16, 8);
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DECL_VARIABLE(vector, uint, 32, 4);
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DECL_VARIABLE(vector, uint, 64, 2);
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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DECL_VARIABLE(vector, float, 16, 8);
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#endif
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DECL_VARIABLE(vector, float, 32, 4);
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DECL_VARIABLE(vector, float, 64, 2);
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DECL_VARIABLE(vector_res, int, 8, 16);
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DECL_VARIABLE(vector_res, int, 16, 8);
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DECL_VARIABLE(vector_res, int, 32, 4);
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DECL_VARIABLE(vector_res, int, 64, 2);
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DECL_VARIABLE(vector_res, uint, 8, 16);
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DECL_VARIABLE(vector_res, uint, 16, 8);
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DECL_VARIABLE(vector_res, uint, 32, 4);
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DECL_VARIABLE(vector_res, uint, 64, 2);
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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DECL_VARIABLE(vector_res, float, 16, 8);
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#endif
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DECL_VARIABLE(vector_res, float, 32, 4);
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DECL_VARIABLE(vector_res, float, 64, 2);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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VLOAD(vector, buffer, q, int, s, 8, 16);
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VLOAD(vector, buffer, q, int, s, 16, 8);
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VLOAD(vector, buffer, q, int, s, 32, 4);
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VLOAD(vector, buffer, q, int, s, 64, 2);
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VLOAD(vector, buffer, q, uint, u, 8, 16);
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VLOAD(vector, buffer, q, uint, u, 16, 8);
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VLOAD(vector, buffer, q, uint, u, 32, 4);
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VLOAD(vector, buffer, q, uint, u, 64, 2);
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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VLOAD(vector, buffer, q, float, f, 16, 8);
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#endif
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VLOAD(vector, buffer, q, float, f, 32, 4);
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VLOAD(vector, buffer, q, float, f, 64, 2);
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/* Apply a binary operator named INSN_NAME. */
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TEST_VPXXXQ(INSN_NAME, int, s, 8, 16);
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TEST_VPXXXQ(INSN_NAME, int, s, 16, 8);
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TEST_VPXXXQ(INSN_NAME, int, s, 32, 4);
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TEST_VPXXXQ(INSN_NAME, int, s, 64, 2);
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TEST_VPXXXQ(INSN_NAME, uint, u, 8, 16);
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TEST_VPXXXQ(INSN_NAME, uint, u, 16, 8);
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TEST_VPXXXQ(INSN_NAME, uint, u, 32, 4);
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TEST_VPXXXQ(INSN_NAME, uint, u, 64, 2);
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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TEST_VPXXXQ(INSN_NAME, float, f, 16, 8);
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#endif
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TEST_VPXXXQ(INSN_NAME, float, f, 32, 4);
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TEST_VPXXXQ(INSN_NAME, float, f, 64, 2);
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CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
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CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
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CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
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CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
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CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
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CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
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CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
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CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
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#endif
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CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
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CHECK_FP(TEST_MSG, float, 64, 2, PRIx64, expected, "");
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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40
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddq.c
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40
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddq.c
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/* { dg-skip-if "" { arm*-*-* } } */
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vpaddq
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#define TEST_MSG "VPADDQ"
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/* Expected results. */
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VECT_VAR_DECL(expected, int, 8, 16) [] = { 0xe1, 0xe5, 0xe9, 0xed,
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0xf1, 0xf5, 0xf9, 0xfd,
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0xe1, 0xe5, 0xe9, 0xed,
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0xf1, 0xf5, 0xf9, 0xfd };
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VECT_VAR_DECL(expected, int, 16, 8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
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0xffe1, 0xffe5, 0xffe9, 0xffed };
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VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xffffffe1, 0xffffffe5,
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0xffffffe1, 0xffffffe5 };
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VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xffffffffffffffe1,
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0xffffffffffffffe1 };
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VECT_VAR_DECL(expected, uint, 8, 16) [] = { 0xe1, 0xe5, 0xe9, 0xed,
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0xf1, 0xf5, 0xf9, 0xfd,
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0xe1, 0xe5, 0xe9, 0xed,
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0xf1, 0xf5, 0xf9, 0xfd };
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VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
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0xffe1, 0xffe5, 0xffe9, 0xffed };
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VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffffe1, 0xffffffe5,
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0xffffffe1, 0xffffffe5};
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VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffffe1,
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0xffffffffffffffe1 };
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#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcfc0, 0xcec0, 0xcdc0, 0xccc0,
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0xcfc0, 0xcec0, 0xcdc0, 0xccc0 };
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#endif
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VECT_VAR_DECL(expected, hfloat, 32, 4) [] = { 0xc1f80000, 0xc1d80000,
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0xc1f80000, 0xc1d80000 };
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VECT_VAR_DECL(expected, hfloat, 64, 2) [] = { 0xc03f000000000000,
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0xc03f000000000000 };
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#include "vpXXXq.inc"
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