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sparc.md (movdi_insn_sp32): Add o/J alternative. 

* config/sparc/sparc.md (movdi_insn_sp32): Add o/J alternative.
        (movdi_insn_sp32_v9): Likewise.  Only allow stx with aligned memory.
        (dimode mem/zero splitter): New.

From-SVN: r52168
This commit is contained in:
Richard Henderson 2002-04-11 10:24:28 -07:00 committed by Richard Henderson
parent af4e7bac5c
commit 7425707da3
2 changed files with 50 additions and 27 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2002-04-11 Richard Henderson <rth@redhat.com>
* config/sparc/sparc.md (movdi_insn_sp32): Add o/J alternative.
(movdi_insn_sp32_v9): Likewise. Only allow stx with aligned memory.
(dimode mem/zero splitter): New.
2002-04-11 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.c (cris_override_options): Tweak error message

71
gcc/config/sparc/sparc.md
View File

@ -1,4 +1,4 @@
;- Machine description for SPARC chip for GNU C compiler
;; Machine description for SPARC chip for GNU C compiler
;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
;; Contributed by Michael Tiemann (tiemann@cygnus.com)
@ -2531,13 +2531,38 @@
(define_insn "*movdi_insn_sp32_v9"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=m,T,U,o,r,r,r,?T,?f,?f,?o,?f")
"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
(match_operand:DI 1 "input_operand"
" J,U,T,r,o,i,r, f, T, o, f, f"))]
" J,J,U,T,r,o,i,r, f, T, o, f, f"))]
"! TARGET_ARCH64 && TARGET_V9
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
stx\\t%%g0, %0
#
std\\t%1, %0
ldd\\t%1, %0
#
#
#
#
std\\t%1, %0
ldd\\t%1, %0
#
#
#"
[(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2")])
(define_insn "*movdi_insn_sp32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
(match_operand:DI 1 "input_operand"
" J,U,T,r,o,i,r, f, T, o, f, f"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
"@
#
std\\t%1, %0
ldd\\t%1, %0
#
@ -2550,30 +2575,7 @@
#
#"
[(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "*,*,*,2,2,2,2,*,*,2,2,2")])
(define_insn "*movdi_insn_sp32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=T,U,o,r,r,r,?T,?f,?f,?o,?f")
(match_operand:DI 1 "input_operand"
" U,T,r,o,i,r, f, T, o, f, f"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
"@
std\\t%1, %0
ldd\\t%1, %0
#
#
#
#
std\\t%1, %0
ldd\\t%1, %0
#
#
#"
[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "*,*,2,2,2,2,*,*,2,2,2")])
(set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_sp64_dbl"
@ -2960,6 +2962,21 @@
DONE;
}")
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(const_int 0))]
"reload_completed
&& (! TARGET_V9
|| (! TARGET_ARCH64
&& ! mem_min_alignment (operands[0], 8)))
&& offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
"
{
emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
DONE;
}")
;; Floating point move insns