config.gcc: Support "goldmont-plus".
2018-05-17 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config.gcc: Support "goldmont-plus". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont-plus". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_GOLDMONT_PLUS. * config/i386/i386.c (m_GOLDMONT_PLUS): Define. (processor_target_table): Add "goldmont-plus". (PTA_GOLDMONT_PLUS): Define. (ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS. (get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS. (fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS. (fold_builtin_cpu): Add "goldmont-plus". (ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS. (ix86_option_override_internal): Add "goldmont-plus". * config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS. (processor_type): Add PROCESSOR_GOLDMONT_PLUS. * config/i386/x86-tune.def: Add m_GOLDMONT_PLUS. * doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS. * config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test goldmont-plus. * gcc.target/i386/funcspec-56.inc: Test arch=goldmont-plus. From-SVN: r260307
This commit is contained in:
Olga Makhotina
Sebastian Peryt
parent
773d0331f7
commit
74b2bb19f3
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@ -1,3 +1,24 @@
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2018-05-17 Olga Makhotina <olga.makhotina@intel.com>
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* config.gcc: Support "goldmont-plus".
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect
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"goldmont-plus".
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle
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PROCESSOR_GOLDMONT_PLUS.
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* config/i386/i386.c (m_GOLDMONT_PLUS): Define.
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(processor_target_table): Add "goldmont-plus".
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(PTA_GOLDMONT_PLUS): Define.
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(ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS.
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(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS.
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(fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS.
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(fold_builtin_cpu): Add "goldmont-plus".
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(ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS.
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(ix86_option_override_internal): Add "goldmont-plus".
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* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS.
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(processor_type): Add PROCESSOR_GOLDMONT_PLUS.
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* config/i386/x86-tune.def: Add m_GOLDMONT_PLUS.
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* doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type.
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2018-05-17 Richard Biener <rguenther@suse.de>
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PR tree-optimization/85757
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@ -640,7 +640,7 @@ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
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core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
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skylake-avx512 cannonlake icelake-client icelake-server skylake goldmont \
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x86-64 native"
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goldmont-plus x86-64 native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -764,6 +764,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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/* Goldmont. */
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cpu = "goldmont";
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break;
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case 0x7a:
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/* Goldmont Plus. */
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cpu = "goldmont-plus";
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break;
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case 0x0f:
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/* Merom. */
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case 0x17:
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@ -868,7 +872,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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cpu = "sandybridge";
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else if (has_sse4_2)
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{
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if (has_xsave)
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if (has_sgx)
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/* Assume Goldmont Plus. */
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cpu = "goldmont-plus";
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else if (has_xsave)
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/* Assume Goldmont. */
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cpu = "goldmont";
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else if (has_movbe)
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@ -178,6 +178,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__goldmont");
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def_or_undef (parse_in, "__goldmont__");
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break;
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case PROCESSOR_GOLDMONT_PLUS:
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def_or_undef (parse_in, "__goldmont_plus");
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def_or_undef (parse_in, "__goldmont_plus__");
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break;
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case PROCESSOR_KNL:
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def_or_undef (parse_in, "__knl");
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def_or_undef (parse_in, "__knl__");
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@ -318,6 +322,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_GOLDMONT:
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def_or_undef (parse_in, "__tune_goldmont__");
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break;
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case PROCESSOR_GOLDMONT_PLUS:
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def_or_undef (parse_in, "__tune_goldmont_plus__");
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break;
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case PROCESSOR_KNL:
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def_or_undef (parse_in, "__tune_knl__");
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break;
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@ -150,6 +150,7 @@ const struct processor_costs *ix86_cost = NULL;
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#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
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#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
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#define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
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#define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS)
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#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL)
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#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE)
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@ -860,6 +861,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{"bonnell", &atom_cost, 16, 15, 16, 7, 16},
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{"silvermont", &slm_cost, 16, 15, 16, 7, 16},
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{"goldmont", &slm_cost, 16, 15, 16, 7, 16},
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{"goldmont-plus", &slm_cost, 16, 15, 16, 7, 16},
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{"knl", &slm_cost, 16, 15, 16, 7, 16},
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{"knm", &slm_cost, 16, 15, 16, 7, 16},
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{"skylake", &skylake_cost, 16, 10, 16, 10, 16},
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@ -3492,6 +3494,8 @@ ix86_option_override_internal (bool main_args_p,
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const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
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| PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
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| PTA_FSGSBASE;
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const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
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| PTA_SGX;
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const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
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| PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
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@ -3568,6 +3572,7 @@ ix86_option_override_internal (bool main_args_p,
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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{"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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{"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
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{"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
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{"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
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{"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
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{"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
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@ -21244,7 +21249,8 @@ ix86_lea_outperforms (rtx_insn *insn, unsigned int regno0, unsigned int regno1,
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/* For Silvermont if using a 2-source or 3-source LEA for
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non-destructive destination purposes, or due to wanting
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ability to use SCALE, the use of LEA is justified. */
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if (TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_INTEL)
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if (TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS
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|| TARGET_INTEL)
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{
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if (has_scale)
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return true;
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@ -32419,10 +32425,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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arg_str = "silvermont";
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priority = P_PROC_SSE4_2;
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break;
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case PROCESSOR_GOLDMONT:
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case PROCESSOR_GOLDMONT:
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arg_str = "goldmont";
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priority = P_PROC_SSE4_2;
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break;
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case PROCESSOR_GOLDMONT_PLUS:
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arg_str = "goldmont-plus";
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priority = P_PROC_SSE4_2;
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break;
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case PROCESSOR_AMDFAM10:
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arg_str = "amdfam10h";
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priority = P_PROC_SSE4_A;
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@ -33128,7 +33138,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_INTEL_COREI7_CANNONLAKE,
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M_INTEL_COREI7_ICELAKE_CLIENT,
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M_INTEL_COREI7_ICELAKE_SERVER,
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M_INTEL_GOLDMONT
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M_INTEL_GOLDMONT,
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M_INTEL_GOLDMONT_PLUS
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};
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static struct _arch_names_table
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@ -33158,6 +33169,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"goldmont", M_INTEL_GOLDMONT},
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{"goldmont-plus", M_INTEL_GOLDMONT_PLUS},
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{"knl", M_INTEL_KNL},
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{"knm", M_INTEL_KNM},
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{"amdfam10h", M_AMDFAM10H},
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@ -50757,8 +50769,8 @@ ix86_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
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/* We need to multiply all vector stmt cost by 1.7 (estimated cost)
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for Silvermont as it has out of order integer pipeline and can execute
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2 scalar instruction per tick, but has in order SIMD pipeline. */
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if ((TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_INTEL)
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&& stmt_info && stmt_info->stmt)
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if ((TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS
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|| TARGET_INTEL) && stmt_info && stmt_info->stmt)
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{
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tree lhs_op = gimple_get_lhs (stmt_info->stmt);
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if (lhs_op && TREE_CODE (TREE_TYPE (lhs_op)) == INTEGER_TYPE)
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@ -390,6 +390,7 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
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#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
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#define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT)
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#define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS)
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#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
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#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
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#define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE)
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@ -2285,6 +2286,7 @@ enum processor_type
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PROCESSOR_BONNELL,
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PROCESSOR_SILVERMONT,
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PROCESSOR_GOLDMONT,
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PROCESSOR_GOLDMONT_PLUS,
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PROCESSOR_KNL,
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PROCESSOR_KNM,
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PROCESSOR_SKYLAKE,
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@ -42,7 +42,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
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| m_GENERIC)
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| m_GOLDMONT_PLUS | m_GENERIC)
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/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
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on modern chips. Preffer stores affecting whole integer register
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@ -50,7 +50,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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value over movb. */
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DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
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m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
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| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
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| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
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| m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
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@ -86,13 +86,15 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
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DEF_TUNE (X86_TUNE_MOVX, "movx",
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m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
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| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
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| m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
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| m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512
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| m_GENERIC)
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/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
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full sized loads. */
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DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
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m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
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| m_KNL | m_KNM | m_GOLDMONT | m_AMD_MULTIPLE | m_GENERIC)
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| m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
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| m_GENERIC)
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/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
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conditional jump instruction for 32 bit TARGET. */
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@ -131,7 +133,7 @@ DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
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DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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| m_GOLDMONT | m_ATHLON_K8)
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| m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
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considered on critical path. */
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@ -193,7 +195,7 @@ DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
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than 4 branch instructions in the 16 byte window. */
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DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
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| m_GOLDMONT | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
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| m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
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/*****************************************************************************/
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/* Integer instruction selection tuning */
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@ -222,23 +224,24 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
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DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
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~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
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| m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
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| m_GENERIC))
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| m_GOLDMONT_PLUS | m_GENERIC))
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/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
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for DFmode copies */
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DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
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~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
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| m_GENERIC))
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| m_GOLDMONT_PLUS | m_GENERIC))
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/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
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will impact LEA instruction selection. */
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DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
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| m_KNM | m_GOLDMONT | m_INTEL)
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| m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
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/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
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DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM)
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
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| m_KNM)
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/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
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vector path on AMD machines.
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@ -255,7 +258,8 @@ DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
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/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
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a conditional move. */
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DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL)
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
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| m_KNM | m_INTEL)
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/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
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as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
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|
|
@ -274,17 +278,18 @@ DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
|
|||
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
|
||||
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
||||
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
|
||||
| m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GENERIC)
|
||||
| m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GOLDMONT_PLUS | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
|
||||
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
|
||||
~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
|
||||
| m_K6 | m_GOLDMONT))
|
||||
| m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS))
|
||||
|
||||
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
|
||||
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
|
||||
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
|
||||
| m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GENERIC)
|
||||
| m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
|
||||
| m_GENERIC)
|
||||
|
||||
/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
|
||||
for bit-manipulation instructions. */
|
||||
|
|
@ -301,7 +306,7 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
|
|||
if-converted sequence to one. */
|
||||
DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
|
||||
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
|
||||
| m_GENERIC)
|
||||
| m_GOLDMONT_PLUS | m_GENERIC)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* 387 instruction selection tuning */
|
||||
|
|
@ -318,7 +323,7 @@ DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
|
|||
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
|
||||
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
|
||||
| m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
|
||||
| m_GOLDMONT | m_GENERIC))
|
||||
| m_GOLDMONT | m_GOLDMONT_PLUS | m_GENERIC))
|
||||
|
||||
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
|
||||
DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
|
||||
|
|
@ -327,7 +332,7 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
|
|||
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
|
||||
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
||||
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
|
||||
| m_GENERIC)
|
||||
| m_GOLDMONT_PLUS | m_GENERIC)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* SSE instruction selection tuning */
|
||||
|
|
@ -342,15 +347,15 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
|
|||
of a sequence loading registers by parts. */
|
||||
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
|
||||
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_AMDFAM10 | m_BDVER
|
||||
| m_BTVER | m_ZNVER1 | m_GENERIC)
|
||||
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_GOLDMONT_PLUS
|
||||
| m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
|
||||
of a sequence loading registers by parts. */
|
||||
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
|
||||
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_BDVER | m_ZNVER1
|
||||
| m_GENERIC)
|
||||
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_GOLDMONT_PLUS
|
||||
| m_BDVER | m_ZNVER1 | m_GENERIC)
|
||||
|
||||
/* Use packed single precision instructions where posisble. I.e. movups instead
|
||||
of movupd. */
|
||||
|
|
@ -387,7 +392,8 @@ DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
|
|||
/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
|
||||
fp converts to destination register. */
|
||||
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
|
||||
m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_INTEL)
|
||||
m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
|
||||
| m_INTEL)
|
||||
|
||||
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
|
||||
from FP to FP. This form of instructions avoids partial write to the
|
||||
|
|
@ -401,11 +407,12 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
|
|||
|
||||
/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
|
||||
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_INTEL)
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
|
||||
| m_GOLDMONT_PLUS | m_INTEL)
|
||||
|
||||
/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
|
||||
DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
|
||||
m_SILVERMONT | m_GOLDMONT | m_INTEL)
|
||||
m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
|
||||
|
||||
/* X86_TUNE_USE_GATHER: Use gather instructions. */
|
||||
DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",
|
||||
|
|
|
|||
|
|
@ -26508,6 +26508,11 @@ Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
|
|||
SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE
|
||||
instruction set support.
|
||||
|
||||
@item goldmont-plus
|
||||
Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
|
||||
PTWRITE, RDPID, SGX and UMIP instruction set support.
|
||||
|
||||
@item knl
|
||||
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2018-05-17 Olga Makhotina <olga.makhotina@intel.com>
|
||||
|
||||
* gcc.target/i386/builtin_target.c: Test goldmont-plus.
|
||||
* gcc.target/i386/funcspec-56.inc: Tests for arch=goldmont-plus.
|
||||
|
||||
2018-05-17 Richard Biener <rguenther@suse.de>
|
||||
|
||||
PR tree-optimization/85757
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
|
|||
/* Goldmont. */
|
||||
assert (__builtin_cpu_is ("goldmont"));
|
||||
break;
|
||||
case 0x7a:
|
||||
/* Goldmont Plus. */
|
||||
assert (__builtin_cpu_is ("goldmont-plus"));
|
||||
break;
|
||||
case 0x57:
|
||||
/* Knights Landing. */
|
||||
assert (__builtin_cpu_is ("knl"));
|
||||
|
|
|
|||
|
|
@ -143,6 +143,7 @@ extern void test_arch_corei7_avx (void) __attribute__((__target__("arch=corei7-
|
|||
extern void test_arch_core_avx2 (void) __attribute__((__target__("arch=core-avx2")));
|
||||
extern void test_arch_silvermont (void) __attribute__((__target__("arch=silvermont")));
|
||||
extern void test_arch_goldmont (void) __attribute__((__target__("arch=goldmont")));
|
||||
extern void test_arch_goldmont_plus (void) __attribute__((__target__("arch=goldmont-plus")));
|
||||
extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
|
||||
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
|
||||
extern void test_arch_skylake (void) __attribute__((__target__("arch=skylake")));
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2018-05-17 Olga Makhotina <olga.makhotina@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS.
|
||||
* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus.
|
||||
|
||||
2018-05-08 Olga Makhotina <olga.makhotina@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT.
|
||||
|
|
|
|||
|
|
@ -145,6 +145,10 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
|
|||
/* Goldmont. */
|
||||
__cpu_model.__cpu_type = INTEL_GOLDMONT;
|
||||
break;
|
||||
case 0x7a:
|
||||
/* Goldmont Plus. */
|
||||
__cpu_model.__cpu_type = INTEL_GOLDMONT_PLUS;
|
||||
break;
|
||||
case 0x57:
|
||||
/* Knights Landing. */
|
||||
__cpu_model.__cpu_type = INTEL_KNL;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ enum processor_types
|
|||
AMDFAM17H,
|
||||
INTEL_KNM,
|
||||
INTEL_GOLDMONT,
|
||||
INTEL_GOLDMONT_PLUS,
|
||||
CPU_TYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue