invoke.texi: Document -march=74kf3_2.
gcc/ 2007-07-03 David Ung <davidu@mips.com> Richard Sandiford <richard@codesourcery.com> * doc/invoke.texi: Document -march=74kf3_2. * config/mips/mips.h (PROCESSOR_74KF3_2): New processor_type. (TUNE_74K): Check for it. * config/mips/mips.c (mips_cpu_info): Add 74kf3_2. (mips_rtx_cost_data): Add an entry for PROCESSOR_74KF3_2. * config/mips/mips.md (cpu): Add 74kf3_2. * config/mips/74k.md (r74k_int_logical, r74k_int_arith, r74k_int_nop) (r74k_int_cmove, r74k_int_mult, r74k_int_mul3, r74k_int_mfhilo) (r74k_int_mthilo, r74k_int_div, r74k_int_call, r74k_int_jump) (r74k_int_load, r74k_int_store, r74k_unknown, r74k_multi): Add 74kf3_2 to the CPU list. (r74kf3_2_fadd, r74kf3_2_fmove, r74kf3_2_fload, r74kf3_2_fstore) (r74kf3_2_fmul_sf, r74kf3_2_fmul_df, r74kf3_2_fdiv_sf) (r74kf3_2_fdiv_df, r74kf3_2_frsqrt_sf, r74kf3_2_frsqrt_df) (r74kf3_2_fcmp, r74kf3_2_fcvt, r74kf3_2_fxfer_to_c1) (r74kf3_2_fxfer_from_c1): New insn reservations. Co-Authored-By: Richard Sandiford <richard@codesourcery.com> From-SVN: r126267
This commit is contained in:
David Ung
Richard Sandiford
parent
bdd77024de
commit
74d4d0244c
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@ -1,3 +1,23 @@
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2007-07-03 David Ung <davidu@mips.com>
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Richard Sandiford <richard@codesourcery.com>
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* doc/invoke.texi: Document -march=74kf3_2.
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* config/mips/mips.h (PROCESSOR_74KF3_2): New processor_type.
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(TUNE_74K): Check for it.
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* config/mips/mips.c (mips_cpu_info): Add 74kf3_2.
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(mips_rtx_cost_data): Add an entry for PROCESSOR_74KF3_2.
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* config/mips/mips.md (cpu): Add 74kf3_2.
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* config/mips/74k.md (r74k_int_logical, r74k_int_arith, r74k_int_nop)
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(r74k_int_cmove, r74k_int_mult, r74k_int_mul3, r74k_int_mfhilo)
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(r74k_int_mthilo, r74k_int_div, r74k_int_call, r74k_int_jump)
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(r74k_int_load, r74k_int_store, r74k_unknown, r74k_multi): Add
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74kf3_2 to the CPU list.
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(r74kf3_2_fadd, r74kf3_2_fmove, r74kf3_2_fload, r74kf3_2_fstore)
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(r74kf3_2_fmul_sf, r74kf3_2_fmul_df, r74kf3_2_fdiv_sf)
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(r74kf3_2_fdiv_df, r74kf3_2_frsqrt_sf, r74kf3_2_frsqrt_df)
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(r74kf3_2_fcmp, r74kf3_2_fcvt, r74kf3_2_fxfer_to_c1)
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(r74kf3_2_fxfer_from_c1): New insn reservations.
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2007-07-03 Richard Sandiford <richard@codesourcery.com>
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David Ung <davidu@mips.com>
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@ -40,74 +40,74 @@
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;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
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;; xor, xori
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(define_insn_reservation "r74k_int_arith" 2
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "arith,const,shift,slt,clz"))
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"r74k_alu")
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(define_insn_reservation "r74k_int_nop" 0
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "nop"))
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"nothing")
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(define_insn_reservation "r74k_int_cmove" 4
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "condmove"))
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"r74k_agen*2")
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;; MDU: fully pipelined multiplier
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;; mult, madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
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(define_insn_reservation "r74k_int_mult" 4
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "imul,imadd"))
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"r74k_alu+r74k_mul")
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;; mul - delivers result to general register in 7 cycles
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(define_insn_reservation "r74k_int_mul3" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "imul3"))
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"r74k_alu+r74k_mul")
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;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
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(define_insn_reservation "r74k_int_mfhilo" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "mfhilo"))
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"r74k_alu+r74k_mul")
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;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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(define_insn_reservation "r74k_int_mthilo" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "mthilo"))
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"r74k_alu+r74k_mul")
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;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,
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;; but is tricky to identify.
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(define_insn_reservation "r74k_int_div" 50
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "idiv"))
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"r74k_alu+r74k_mul*50")
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;; call
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(define_insn_reservation "r74k_int_call" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "call"))
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"r74k_agen")
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;; branch/jump
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(define_insn_reservation "r74k_int_jump" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "branch,jump"))
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"r74k_agen")
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;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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;; prefetch: prefetch, prefetchx
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(define_insn_reservation "r74k_int_load" 3
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "load,prefetch,prefetchx"))
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"r74k_agen")
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;; stores
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(define_insn_reservation "r74k_int_store" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(and (eq_attr "type" "store")
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(eq_attr "mode" "!unknown")))
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"r74k_agen")
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@ -118,12 +118,12 @@
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;; affects scheduling via log links, but not used here).
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;;
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(define_insn_reservation "r74k_unknown" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "unknown"))
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"r74k_alu")
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(define_insn_reservation "r74k_multi" 10
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "multi"))
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"(r74k_alu+r74k_agen)*10")
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@ -170,6 +170,11 @@
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(eq_attr "type" "fadd,fabs,fneg"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fadd" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fadd,fabs,fneg"))
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"r74k_fpu_arith")
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;; fmove, fcmove
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(define_insn_reservation "r74kf1_1_fmove" 4
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(and (eq_attr "cpu" "74kf1_1")
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@ -181,6 +186,11 @@
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(eq_attr "type" "fmove"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fmove" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fmove"))
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"r74k_fpu_arith")
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;; fload
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(define_insn_reservation "r74kf1_1_fload" 4
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(and (eq_attr "cpu" "74kf1_1")
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@ -192,6 +202,11 @@
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(eq_attr "type" "fpload,fpidxload"))
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"r74k_agen+(r74k_fpu_ldst*2)")
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(define_insn_reservation "r74kf3_2_fload" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fpload,fpidxload"))
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"r74k_agen+r74k_fpu_ldst")
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;; fstore
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(define_insn_reservation "r74kf1_1_fstore" 1
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(and (eq_attr "cpu" "74kf1_1")
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@ -203,6 +218,11 @@
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(eq_attr "type" "fpstore,fpidxstore"))
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"r74k_agen+(r74k_fpu_ldst*2)")
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(define_insn_reservation "r74kf3_2_fstore" 1
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fpstore,fpidxstore"))
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"r74k_agen+r74k_fpu_ldst")
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;; fmul, fmadd
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(define_insn_reservation "r74kf1_1_fmul_sf" 4
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(and (eq_attr "cpu" "74kf1_1")
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@ -216,6 +236,12 @@
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fmul_sf" 6
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf1_1_fmul_df" 5
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(and (eq_attr "cpu" "74kf1_1")
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(and (eq_attr "type" "fmul,fmadd")
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@ -228,6 +254,12 @@
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*4")
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(define_insn_reservation "r74kf3_2_fmul_df" 7
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*2")
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;; fdiv, fsqrt
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(define_insn_reservation "r74kf1_1_fdiv_sf" 17
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(and (eq_attr "cpu" "74kf1_1")
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@ -241,6 +273,12 @@
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*28")
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(define_insn_reservation "r74kf3_2_fdiv_sf" 25
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*14")
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(define_insn_reservation "r74kf1_1_fdiv_df" 32
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(and (eq_attr "cpu" "74kf1_1")
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(and (eq_attr "type" "fdiv,fsqrt")
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@ -253,6 +291,12 @@
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*58")
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(define_insn_reservation "r74kf3_2_fdiv_df" 48
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*29")
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;; frsqrt
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(define_insn_reservation "r74kf1_1_frsqrt_sf" 17
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(and (eq_attr "cpu" "74kf1_1")
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@ -266,6 +310,12 @@
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*28")
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(define_insn_reservation "r74kf3_2_frsqrt_sf" 25
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*14")
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(define_insn_reservation "r74kf1_1_frsqrt_df" 36
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(and (eq_attr "cpu" "74kf1_1")
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(and (eq_attr "type" "frsqrt")
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@ -278,6 +328,12 @@
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*62")
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(define_insn_reservation "r74kf3_2_frsqrt_df" 54
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*31")
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;; fcmp
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(define_insn_reservation "r74kf1_1_fcmp" 4
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(and (eq_attr "cpu" "74kf1_1")
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@ -289,6 +345,11 @@
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(eq_attr "type" "fcmp"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fcmp" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fcmp"))
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"r74k_fpu_arith")
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;; fcvt
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(define_insn_reservation "r74kf1_1_fcvt" 4
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "fcvt"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fcvt" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fcvt"))
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"r74k_fpu_arith")
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;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
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(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
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(and (eq_attr "cpu" "74kf1_1")
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@ -311,6 +377,11 @@
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(eq_attr "type" "mtc"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "mtc"))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "mfc"))
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@ -320,3 +391,8 @@
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(and (eq_attr "cpu" "74kf2_1")
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(eq_attr "type" "mfc"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "mfc"))
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"r74k_fpu_arith")
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@ -799,6 +799,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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{ "74kf1_1", PROCESSOR_74KF1_1, 33 },
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{ "74kfx", PROCESSOR_74KF1_1, 33 },
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{ "74kx", PROCESSOR_74KF1_1, 33 },
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{ "74kf3_2", PROCESSOR_74KF3_2, 33 },
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/* MIPS64 */
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{ "5kc", PROCESSOR_5KC, 64 },
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@ -978,6 +979,19 @@ static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* 74KF3_2 */
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COSTS_N_INSNS (6), /* fp_add */
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COSTS_N_INSNS (6), /* fp_mult_sf */
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COSTS_N_INSNS (7), /* fp_mult_df */
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COSTS_N_INSNS (25), /* fp_div_sf */
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COSTS_N_INSNS (48), /* fp_div_df */
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COSTS_N_INSNS (5), /* int_mult_si */
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COSTS_N_INSNS (5), /* int_mult_di */
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COSTS_N_INSNS (41), /* int_div_si */
|
||||
COSTS_N_INSNS (41), /* int_div_di */
|
||||
1, /* branch_cost */
|
||||
4 /* memory_latency */
|
||||
},
|
||||
{ /* M4k */
|
||||
DEFAULT_COSTS
|
||||
},
|
||||
|
|
@ -10798,6 +10812,7 @@ mips_issue_rate (void)
|
|||
case PROCESSOR_74KC:
|
||||
case PROCESSOR_74KF2_1:
|
||||
case PROCESSOR_74KF1_1:
|
||||
case PROCESSOR_74KF3_2:
|
||||
case PROCESSOR_R4130:
|
||||
case PROCESSOR_R5400:
|
||||
case PROCESSOR_R5500:
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ enum processor_type {
|
|||
PROCESSOR_74KC,
|
||||
PROCESSOR_74KF2_1,
|
||||
PROCESSOR_74KF1_1,
|
||||
PROCESSOR_74KF3_2,
|
||||
PROCESSOR_M4K,
|
||||
PROCESSOR_R3900,
|
||||
PROCESSOR_R6000,
|
||||
|
|
@ -250,7 +251,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
|
|||
|| mips_tune == PROCESSOR_SB1A)
|
||||
#define TUNE_74K (mips_tune == PROCESSOR_74KC \
|
||||
|| mips_tune == PROCESSOR_74KF2_1 \
|
||||
|| mips_tune == PROCESSOR_74KF1_1)
|
||||
|| mips_tune == PROCESSOR_74KF1_1 \
|
||||
|| mips_tune == PROCESSOR_74KF3_2)
|
||||
|
||||
/* True if the pre-reload scheduler should try to create chains of
|
||||
multiply-add or multiply-subtract instructions. For example,
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@
|
|||
;; Attribute describing the processor. This attribute must match exactly
|
||||
;; with the processor_type enumeration in mips.h.
|
||||
(define_attr "cpu"
|
||||
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
|
||||
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
|
||||
(const (symbol_ref "mips_tune")))
|
||||
|
||||
;; The type of hardware hazard associated with this instruction.
|
||||
|
|
|
|||
|
|
@ -11428,7 +11428,7 @@ The processor names are:
|
|||
@samp{24kc}, @samp{24kf2_1}, @samp{24kf1_1},
|
||||
@samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1},
|
||||
@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1},
|
||||
@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1},
|
||||
@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
|
||||
@samp{m4k},
|
||||
@samp{orion},
|
||||
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
|
||||
|
|
@ -11447,11 +11447,13 @@ In processor names, a final @samp{000} can be abbreviated as @samp{k}
|
|||
@samp{vr} may be written @samp{r}.
|
||||
|
||||
Names of the form @samp{@var{n}f2_1} refer to processors with
|
||||
FPUs clocked at half the rate of the core. Names of the form
|
||||
FPUs clocked at half the rate of the core, names of the form
|
||||
@samp{@var{n}f1_1} refer to processors with FPUs clocked at the same
|
||||
rate as the core. For compatibility reasons, @samp{@var{n}f} is
|
||||
accepted as a synonym for @samp{@var{n}f2_1} while @samp{@var{n}x} and
|
||||
@samp{@var{b}fx} are accepted as synonyms for @samp{@var{n}f1_1}.
|
||||
rate as the core, and names of the form @samp{@var{n}f3_2} refer to
|
||||
processors with FPUs clocked a ratio of 3:2 with respect to the core.
|
||||
For compatibility reasons, @samp{@var{n}f} is accepted as a synonym
|
||||
for @samp{@var{n}f2_1} while @samp{@var{n}x} and @samp{@var{b}fx} are
|
||||
accepted as synonyms for @samp{@var{n}f1_1}.
|
||||
|
||||
GCC defines two macros based on the value of this option. The first
|
||||
is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
|
||||
|
|
|
|||
Loading…
Reference in New Issue