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arm.c (arm_dwarf_register_span): Take into account the endianness of the D registers for the legacy encodings.

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* config/arm/arm.c (arm_dwarf_register_span): Take into account the
	endianness of the D registers for the legacy encodings.

From-SVN: r205118
This commit is contained in:
Eric Botcazou 2013-11-20 13:58:12 +00:00 committed by Eric Botcazou
parent c34fb19832
commit 74e25e34f8
2 changed files with 31 additions and 7 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-11-20 Eric Botcazou <ebotcazou@adacore.com>
* config/arm/arm.c (arm_dwarf_register_span): Take into account the
endianness of the D registers for the legacy encodings.
2013-11-20 Richard Earnshaw <rearnsha@arm.com>
PR rtl-optimization/54300

33
gcc/config/arm/arm.c
View File

@ -27992,10 +27992,11 @@ arm_dbx_register_number (unsigned int regno)
static rtx
arm_dwarf_register_span (rtx rtl)
{
enum machine_mode mode;
unsigned regno;
rtx parts[8];
int nregs;
int i;
rtx p;
regno = REGNO (rtl);
if (!IS_VFP_REGNUM (regno))
@ -28008,15 +28009,33 @@ arm_dwarf_register_span (rtx rtl)
corresponding D register. Until GDB supports this, we shall use the
legacy encodings. We also use these encodings for D0-D15 for
compatibility with older debuggers. */
if (VFP_REGNO_OK_FOR_SINGLE (regno))
mode = GET_MODE (rtl);
if (GET_MODE_SIZE (mode) < 8)
return NULL_RTX;
nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8;
p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
for (i = 0; i < nregs; i++)
XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i);
if (VFP_REGNO_OK_FOR_SINGLE (regno))
{
nregs = GET_MODE_SIZE (mode) / 4;
for (i = 0; i < nregs; i += 2)
if (TARGET_BIG_END)
{
parts[i] = gen_rtx_REG (SImode, regno + i + 1);
parts[i + 1] = gen_rtx_REG (SImode, regno + i);
}
else
{
parts[i] = gen_rtx_REG (SImode, regno + i);
parts[i + 1] = gen_rtx_REG (SImode, regno + i + 1);
}
}
else
{
nregs = GET_MODE_SIZE (mode) / 8;
for (i = 0; i < nregs; i++)
parts[i] = gen_rtx_REG (DImode, regno + i);
}
return p;
return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nregs , parts));
}
#if ARM_UNWIND_INFO