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mips.md (move_type): Add arith.

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* config/mips/mips.md (move_type): Add arith.
	(type): Handle arith.
	(zero_extendsidi2): Rename this into ...
	(*zero_extendsidi2): ... this.  Don't match if ISA_HAS_EXT_INS.
	(zero_extendsidi2): New expander.
	(*zero_extendsidi2_dext): New pattern.

testsuite/
	* gcc.target/mips/ext-3.c: New test.

From-SVN: r149829
This commit is contained in:
Adam Nemet 2009-07-20 19:01:45 +00:00 committed by Adam Nemet
parent 621114bc7b
commit 752fd2a892
4 changed files with 46 additions and 3 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2009-07-20 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.md (move_type): Add arith.
(type): Handle arith.
(zero_extendsidi2): Rename this into ...
(*zero_extendsidi2): ... this. Don't match if ISA_HAS_EXT_INS.
(zero_extendsidi2): New expander.
(*zero_extendsidi2_dext): New pattern.
2009-07-20 Nick Clifton <nickc@redhat.com>
* config.gcc (mips64-*-*): Add definition of tm_defines in order

22
gcc/config/mips/mips.md
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@ -313,7 +313,7 @@
;; scheduling type to be "multi" instead.
(define_attr "move_type"
"unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
const,constN,signext,arith,sll0,andi,loadpool,shift_shift,lui_movf"
(const_string "unknown"))
;; Main data type used by the insn
@ -408,6 +408,7 @@
(eq_attr "move_type" "fmove") (const_string "fmove")
(eq_attr "move_type" "loadpool") (const_string "load")
(eq_attr "move_type" "signext") (const_string "signext")
(eq_attr "move_type" "arith") (const_string "arith")
(eq_attr "move_type" "sll0") (const_string "shift")
(eq_attr "move_type" "andi") (const_string "logical")
@ -2746,10 +2747,15 @@
;; Extension insns.
(define_insn_and_split "zero_extendsidi2"
(define_expand "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
"TARGET_64BIT")
(define_insn_and_split "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
"TARGET_64BIT"
"TARGET_64BIT && !ISA_HAS_EXT_INS"
"@
#
lwu\t%0,%1"
@ -2762,6 +2768,16 @@
[(set_attr "move_type" "shift_shift,load")
(set_attr "mode" "DI")])
(define_insn "*zero_extendsidi2_dext"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
"TARGET_64BIT && ISA_HAS_EXT_INS"
"@
dext\t%0,%1,0,32
lwu\t%0,%1"
[(set_attr "move_type" "arith,load")
(set_attr "mode" "DI")])
;; Combine is not allowed to convert this insn into a zero_extendsidi2
;; because of TRULY_NOOP_TRUNCATION.

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2009-07-20 Adam Nemet <anemet@caviumnetworks.com>
* gcc.target/mips/ext-3.c: New test.
2009-07-20 Jakub Jelinek <jakub@redhat.com>
* gcc.dg/builtin-object-size-6.c: Adjust expected values.

14
gcc/testsuite/gcc.target/mips/ext-3.c Normal file
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@ -0,0 +1,14 @@
/* For MIPS64r2 use DEXT rather than DSLL/DSRL to zero-extend. */
/* { dg-do compile } */
/* { dg-options "-O isa_rev>=2 -mgp64" } */
/* { dg-final { scan-assembler "\tdext\t" } } */
/* { dg-final { scan-assembler-not "sll" } } */
unsigned long long
f (unsigned *i)
{
unsigned j = *i;
j >>= 1; /* enforce this is all done in SI mode */
j++; /* don't merge the shift and the extension */
return j;
}