arm.h (REGISTER_MOVE_COST, [...]): Remove.
* config/arm/arm.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove. * config/arm/arm.c (arm_memory_move_cost, arm_register_move_cost): New functions. (TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define. From-SVN: r182369
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@ -1,3 +1,10 @@
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2011-12-15 Anatoly Sokolov <aesok@post.ru>
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* config/arm/arm.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove.
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* config/arm/arm.c (arm_memory_move_cost, arm_register_move_cost):
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New functions.
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(TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define.
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2011-12-15 Richard Guenther <rguenther@suse.de>
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PR lto/51564
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@ -164,6 +164,8 @@ static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool
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static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
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static bool arm_rtx_costs (rtx, int, int, int, int *, bool);
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static int arm_address_cost (rtx, bool);
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static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
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static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
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static bool arm_memory_load_p (rtx);
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static bool arm_cirrus_insn_p (rtx);
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static void cirrus_reorg (rtx);
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@ -363,6 +365,12 @@ static const struct attribute_spec arm_attribute_table[] =
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#undef TARGET_SCHED_ADJUST_COST
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#define TARGET_SCHED_ADJUST_COST arm_adjust_cost
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#undef TARGET_REGISTER_MOVE_COST
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#define TARGET_REGISTER_MOVE_COST arm_register_move_cost
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#undef TARGET_MEMORY_MOVE_COST
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#define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
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#undef TARGET_ENCODE_SECTION_INFO
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#ifdef ARM_PE
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#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
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@ -8484,6 +8492,63 @@ fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
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return true;
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}
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/* Implement TARGET_REGISTER_MOVE_COST.
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Moves between FPA_REGS and GENERAL_REGS are two memory insns.
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Moves between VFP_REGS and GENERAL_REGS are a single insn, but
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it is typically more expensive than a single memory access. We set
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the cost to less than two memory accesses so that floating
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point to integer conversion does not go through memory. */
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int
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arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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reg_class_t from, reg_class_t to)
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{
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if (TARGET_32BIT)
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{
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if ((from == FPA_REGS && to != FPA_REGS)
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|| (from != FPA_REGS && to == FPA_REGS))
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return 20;
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else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
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|| (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
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return 15;
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else if ((from == IWMMXT_REGS && to != IWMMXT_REGS)
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|| (from != IWMMXT_REGS && to == IWMMXT_REGS))
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return 4;
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else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS)
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return 20;
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else if ((from == CIRRUS_REGS && to != CIRRUS_REGS)
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|| (from != CIRRUS_REGS && to == CIRRUS_REGS))
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return 20;
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else
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return 2;
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}
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else
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{
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if (from == HI_REGS || to == HI_REGS)
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return 4;
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else
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return 2;
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}
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}
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/* Implement TARGET_MEMORY_MOVE_COST. */
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int
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arm_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
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bool in ATTRIBUTE_UNUSED)
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{
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if (TARGET_32BIT)
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return 10;
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else
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{
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if (GET_MODE_SIZE (mode) < 4)
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return 8;
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else
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return ((2 * GET_MODE_SIZE (mode)) * (rclass == LO_REGS ? 1 : 2));
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}
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}
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/* This function implements the target macro TARGET_SCHED_ADJUST_COST.
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It corrects the value of COST based on the relationship between
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INSN and DEP through the dependence LINK. It returns the new
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@ -1281,26 +1281,6 @@ do { \
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/* If defined, gives a class of registers that cannot be used as the
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operand of a SUBREG that changes the mode of the object illegally. */
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/* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
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Moves between VFP_REGS and GENERAL_REGS are a single insn, but
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it is typically more expensive than a single memory access. We set
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the cost to less than two memory accesses so that floating
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point to integer conversion does not go through memory. */
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#define REGISTER_MOVE_COST(MODE, FROM, TO) \
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(TARGET_32BIT ? \
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((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
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(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
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IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
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!IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
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(FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
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(FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
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(FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
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(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
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(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
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2) \
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: \
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((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
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/* Stack layout; function entry, exit and calling. */
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@ -1953,12 +1933,6 @@ typedef struct
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( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
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|| (X) == arg_pointer_rtx)
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/* Moves to and from memory are quite expensive */
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#define MEMORY_MOVE_COST(M, CLASS, IN) \
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(TARGET_32BIT ? 10 : \
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((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
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* (CLASS == LO_REGS ? 1 : 2)))
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/* Try to generate sequences that don't involve branches, we can then use
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conditional instructions */
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#define BRANCH_COST(speed_p, predictable_p) \
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