From 75d2580c0cc46323711df161593281bceb50a99d Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Sat, 14 Jun 2003 15:54:02 +0000 Subject: [PATCH] re PR target/11183 ([arm] ICE in change_address_1 (3.3) / subreg_hard_regno (3.4)) PR target/11183 * arm.h (CANNOT_CHANGE_MODE_CLASS): Define. From-SVN: r67947 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/arm.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fd2c2949e1f..4713756af4c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2003-06-14 Richard Earnshaw + + PR target/11183 + * arm.h (CANNOT_CHANGE_MODE_CLASS): Define. + 2003-06-14 Roger Sayle * opts.sh: Work around a mysterious feature in cygwin's gawk diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index cffdd3ba056..acec706d995 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1146,6 +1146,12 @@ enum reg_class or could index an array. */ #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) +/* FPA registers can't do dubreg as all values are reformatted to internal + precision. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0) + /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)