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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode. 

* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
	MODE_PARTIAL_INT mode.
	* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
	* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
	for CONST_INTs.
	(hard_regno_mode_ok): V2PDImode is ok for accumulators.
	* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
	V2PDImode.
	* config/bfin/predicates.md (const01_operand, vec_shift_operand):
	New predicates.
	* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
	New constants.
	(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
	MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
	MACFLAG_IH): Likewise.
	(movstricthi_1): Renamed from "*movstricthi".
	(load_accumulator, load_accumulator_pair, movsi_insv, insv,
	ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
	abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
	movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
	movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
	movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
	addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
	sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
	addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
	mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
	ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
	flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
	flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
	flag_macv2hi_parts, flag_macv2hi_parts_acconly,
	flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.

From-SVN: r113245
This commit is contained in:
Bernd Schmidt 2006-04-25 11:49:27 +00:00 committed by Bernd Schmidt
parent ec23e15b4c
commit 75d8b2d014
7 changed files with 1049 additions and 27 deletions
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34
gcc/ChangeLog
View File

@ -1,3 +1,37 @@
2006-04-25 Bernd Schmidt <bernd.schmidt@analog.com>
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
MODE_PARTIAL_INT mode.
* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
for CONST_INTs.
(hard_regno_mode_ok): V2PDImode is ok for accumulators.
* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
V2PDImode.
* config/bfin/predicates.md (const01_operand, vec_shift_operand):
New predicates.
* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
New constants.
(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
MACFLAG_IH): Likewise.
(movstricthi_1): Renamed from "*movstricthi".
(load_accumulator, load_accumulator_pair, movsi_insv, insv,
ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
flag_macv2hi_parts, flag_macv2hi_parts_acconly,
flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
2006-04-24 Geoffrey Keating <geoffk@apple.com>
* dwarf2out.c (verify_marks_clear): New.

4
gcc/config/bfin/bfin-modes.def
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@ -22,4 +22,8 @@
/* PDImode for the 40 bit accumulators. */
PARTIAL_INT_MODE (DI);
/* Two of those - covering both accumulators for vector multiplications. */
VECTOR_MODE (INT, PDI, 2);
VECTOR_MODE (INT, HI, 2); /* V2HI */
VECTOR_MODE (INT, SI, 2); /* V2SI - occasionally used. */

55
gcc/config/bfin/bfin.c
View File

@ -1259,9 +1259,60 @@ print_operand (FILE *file, rtx x, char code)
break;
case CONST_INT:
if (code == 'M')
{
switch (INTVAL (x))
{
case MACFLAG_NONE:
break;
case MACFLAG_FU:
fputs ("(FU)", file);
break;
case MACFLAG_T:
fputs ("(T)", file);
break;
case MACFLAG_TFU:
fputs ("(TFU)", file);
break;
case MACFLAG_W32:
fputs ("(W32)", file);
break;
case MACFLAG_IS:
fputs ("(IS)", file);
break;
case MACFLAG_IU:
fputs ("(IU)", file);
break;
case MACFLAG_IH:
fputs ("(IH)", file);
break;
case MACFLAG_M:
fputs ("(M)", file);
break;
case MACFLAG_ISS2:
fputs ("(ISS2)", file);
break;
case MACFLAG_S2RND:
fputs ("(S2RND)", file);
break;
default:
gcc_unreachable ();
}
break;
}
else if (code == 'b')
{
if (INTVAL (x) == 0)
fputs ("+=", file);
else if (INTVAL (x) == 1)
fputs ("-=", file);
else
gcc_unreachable ();
break;
}
/* Moves to half registers with d or h modifiers always use unsigned
constants. */
if (code == 'd')
else if (code == 'd')
x = GEN_INT ((INTVAL (x) >> 16) & 0xffff);
else if (code == 'h')
x = GEN_INT (INTVAL (x) & 0xffff);
@ -1672,7 +1723,7 @@ hard_regno_mode_ok (int regno, enum machine_mode mode)
return D_REGNO_P (regno);
if (class == CCREGS)
return mode == BImode;
if (mode == PDImode)
if (mode == PDImode || mode == V2PDImode)
return regno == REG_A0 || regno == REG_A1;
if (mode == SImode
&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))

10
gcc/config/bfin/bfin.h
View File

@ -509,12 +509,14 @@ enum reg_class
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define HARD_REGNO_NREGS(REGNO, MODE) \
((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) \
? 1 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
: (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
: CLASS_MAX_NREGS (GENERAL_REGS, MODE))
/* A C expression that is nonzero if hard register TO can be
considered for use as a rename register for FROM register */

961
gcc/config/bfin/bfin.md
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File diff suppressed because it is too large Load Diff

8
gcc/config/bfin/predicates.md
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@ -56,6 +56,14 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
(define_predicate "const01_operand"
(match_test "op == const0_rtx || op == const1_rtx"))
(define_predicate "vec_shift_operand"
(ior (and (match_code "const_int")
(match_test "INTVAL (op) >= -16 && INTVAL (op) < 15"))
(match_operand 0 "register_operand")))
;; Like register_operand, but make sure that hard regs have a valid mode.
(define_predicate "valid_reg_operand"
(match_operand 0 "register_operand")

4
gcc/genmodes.c
View File

@ -635,7 +635,9 @@ make_vector_mode (enum mode_class bclass,
error ("%s:%d: no mode \"%s\"", file, line, base);
return;
}
if (component->cl != bclass)
if (component->cl != bclass
&& (component->cl != MODE_PARTIAL_INT
|| bclass != MODE_INT))
{
error ("%s:%d: mode \"%s\" is not class %s",
file, line, base, mode_class_names[bclass] + 5);