From 760f82dbb7595a30206b04445240effad725d82f Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 7 Mar 2017 09:11:30 +0100 Subject: [PATCH] re PR rtl-optimization/79901 (ICE in prepare_cmp_insn, at optabs.c:3904) PR rtl-optimization/79901 * config/i386/sse.md (*avx512bw_3): Renamed to ... (*avx512f_3): ... this. (3 with maxmin code iterator): Use VI8_AVX2_AVX512F iterator instead of VI8_AVX2_AVX512BW. * gcc.target/i386/pr79901.c: New test. From-SVN: r245947 --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/sse.md | 10 +++++----- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.target/i386/pr79901.c | 22 ++++++++++++++++++++++ 4 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr79901.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index efeee1a1796..227b48aca6a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-03-07 Jakub Jelinek + PR rtl-optimization/79901 + * config/i386/sse.md (*avx512bw_3): Renamed to + ... + (*avx512f_3): ... this. + (3 with maxmin code iterator): Use VI8_AVX2_AVX512F + iterator instead of VI8_AVX2_AVX512BW. + PR rtl-optimization/79901 * expr.c (expand_expr_real_2): For vector MIN/MAX, if there is no min/max expander, expand it using expand_vec_cond_expr. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ac63235e38f..5cca4f1d4fd 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10841,7 +10841,7 @@ "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*avx512bw_3" +(define_insn "*avx512f_3" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (maxmin:VI48_AVX512VL (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v") @@ -10865,10 +10865,10 @@ (set_attr "mode" "")]) (define_expand "3" - [(set (match_operand:VI8_AVX2_AVX512BW 0 "register_operand") - (maxmin:VI8_AVX2_AVX512BW - (match_operand:VI8_AVX2_AVX512BW 1 "register_operand") - (match_operand:VI8_AVX2_AVX512BW 2 "register_operand")))] + [(set (match_operand:VI8_AVX2_AVX512F 0 "register_operand") + (maxmin:VI8_AVX2_AVX512F + (match_operand:VI8_AVX2_AVX512F 1 "register_operand") + (match_operand:VI8_AVX2_AVX512F 2 "register_operand")))] "TARGET_SSE4_2" { if (TARGET_AVX512F diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9c8b87e90c7..b927b5a2976 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2017-03-07 Jakub Jelinek + PR rtl-optimization/79901 + * gcc.target/i386/pr79901.c: New test. + PR sanitizer/79897 * c-c++-common/ubsan/pr79897.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr79901.c b/gcc/testsuite/gcc.target/i386/pr79901.c new file mode 100644 index 00000000000..6fdcf767362 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79901.c @@ -0,0 +1,22 @@ +/* PR rtl-optimization/79901 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx512f -fno-ssa-phiopt" } */ + +unsigned int +foo (const unsigned long long x) +{ + if (x < 0) + return 0; + else if ( x > ~0U) + return ~0U; + else + return (unsigned int) x; +} + +void +bar (unsigned x, unsigned int *y, unsigned int z) +{ + unsigned i; + for (i = 0; i < x; i++) + y[i] = foo (y[i] * (unsigned long long) z); +}