[AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, the CPU core will not execute the unnecessary DCache clean or Icache Invalidation instructions. 2019-09-25 Shaokun Zhang <zhangshaokun@hisilicon.com> * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for CTR_EL0.IDC and CTR_EL0.DIC. From-SVN: r276122
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@ -1,3 +1,8 @@
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2019-09-25 Shaokun Zhang <zhangshaokun@hisilicon.com>
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* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for
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CTR_EL0.IDC and CTR_EL0.DIC.
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2019-09-20 Christophe Lyon <christophe.lyon@st.com>
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2019-09-20 Christophe Lyon <christophe.lyon@st.com>
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Revert:
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Revert:
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@ -23,6 +23,9 @@ a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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<http://www.gnu.org/licenses/>. */
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#define CTR_IDC_SHIFT 28
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#define CTR_DIC_SHIFT 29
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void __aarch64_sync_cache_range (const void *, const void *);
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void __aarch64_sync_cache_range (const void *, const void *);
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void
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void
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@ -41,6 +44,10 @@ __aarch64_sync_cache_range (const void *base, const void *end)
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icache_lsize = 4 << (cache_info & 0xF);
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icache_lsize = 4 << (cache_info & 0xF);
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dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
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dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
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/* If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification is
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not required for instruction to data coherence. */
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if (((cache_info >> CTR_IDC_SHIFT) & 0x1) == 0x0) {
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/* Loop over the address range, clearing one cache line at once.
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/* Loop over the address range, clearing one cache line at once.
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Data cache must be flushed to unification first to make sure the
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Data cache must be flushed to unification first to make sure the
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instruction cache fetches the updated data. 'end' is exclusive,
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instruction cache fetches the updated data. 'end' is exclusive,
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@ -55,9 +62,14 @@ __aarch64_sync_cache_range (const void *base, const void *end)
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:
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:
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: "r" (address)
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: "r" (address)
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: "memory");
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: "memory");
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}
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asm volatile ("dsb\tish" : : : "memory");
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asm volatile ("dsb\tish" : : : "memory");
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/* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point of
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Unification is not required for instruction to data coherence. */
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if (((cache_info >> CTR_DIC_SHIFT) & 0x1) == 0x0) {
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/* Make the start address of the loop cache aligned. */
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/* Make the start address of the loop cache aligned. */
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address = (const char*) ((__UINTPTR_TYPE__) base
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address = (const char*) ((__UINTPTR_TYPE__) base
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& ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
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& ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
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@ -68,5 +80,8 @@ __aarch64_sync_cache_range (const void *base, const void *end)
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: "r" (address)
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: "r" (address)
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: "memory");
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: "memory");
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asm volatile ("dsb\tish; isb" : : : "memory");
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asm volatile ("dsb\tish" : : : "memory");
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}
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asm volatile("isb" : : : "memory");
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}
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}
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