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[AArch64][SVE2] Shift-Right Accumulate combine patterns 

This patch adds combining support for SVE2's shift-right accumulate
instructions.

2019-09-27  Yuliang Wang  <yuliang.wang@arm.com>

gcc/
	* config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>):
	New combine pattern.

gcc/testsuite/
	* gcc.target/aarch64/sve2/shracc_1.c: New test.

From-SVN: r276174
This commit is contained in:
Yuliang Wang 2019-09-27 08:10:30 +00:00 committed by Richard Sandiford
parent 639a28ba6e
commit 76bb5af63d
4 changed files with 67 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2019-09-27 Yuliang Wang <yuliang.wang@arm.com>
* config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>):
New combine pattern.
2019-09-26 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead

19
gcc/config/aarch64/aarch64-sve2.md
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@ -123,3 +123,22 @@
}
)
;; Unpredicated signed / unsigned shift-right accumulate.
(define_insn_and_rewrite "*aarch64_sve2_sra<mode>"
[(set (match_operand:SVE_I 0 "register_operand" "=w")
(plus:SVE_I
(unspec:SVE_I
[(match_operand 4)
(SHIFTRT:SVE_I
(match_operand:SVE_I 2 "register_operand" "w")
(match_operand:SVE_I 3 "aarch64_simd_rshift_imm" "Dr"))]
UNSPEC_PRED_X)
(match_operand:SVE_I 1 "register_operand" "0")))]
"TARGET_SVE2"
"<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3"
"&& !CONSTANT_P (operands[4])"
{
operands[4] = CONSTM1_RTX (<VPRED>mode);
}
)

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2019-09-27 Yuliang Wang <yuliang.wang@arm.com>
* gcc.target/aarch64/sve2/shracc_1.c: New test.
2019-09-26 Eric Botcazou <ebotcazou@adacore.com>
* gcc.dg/cpp/ucs.c: Add test for new warning and adjust.

39
gcc/testsuite/gcc.target/aarch64/sve2/shracc_1.c Normal file
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@ -0,0 +1,39 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details --save-temps" } */
#include <stdint.h>
#define SHRACC(TYPE,SHIFT) \
void __attribute__ ((noinline, noclone)) \
f_##TYPE##_##SHIFT \
(TYPE *restrict a, TYPE *restrict b, int n) \
{ \
for (int i = 0; i < n; i++) \
a[i] += b[i] >> (SHIFT); \
}
SHRACC (int8_t, 5);
SHRACC (int16_t, 14);
SHRACC (int32_t, 19);
SHRACC (int64_t, 27);
SHRACC (uint8_t, 2);
SHRACC (uint16_t, 6);
SHRACC (uint32_t, 24);
SHRACC (uint64_t, 53);
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */
/* { dg-final { scan-assembler-not {\tasr\t} } } */
/* { dg-final { scan-assembler-not {\tlsr\t} } } */
/* { dg-final { scan-assembler-not {\tadd\t} } } */
/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.h, z[0-9]+\.h, #14\n} 1 } } */
/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.s, z[0-9]+\.s, #19\n} 1 } } */
/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.d, z[0-9]+\.d, #27\n} 1 } } */
/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 } } */
/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 } } */
/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.s, z[0-9]+\.s, #24\n} 1 } } */
/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.d, z[0-9]+\.d, #53\n} 1 } } */