[AArch64][SVE2] Shift-Right Accumulate combine patterns
This patch adds combining support for SVE2's shift-right accumulate instructions. 2019-09-27 Yuliang Wang <yuliang.wang@arm.com> gcc/ * config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>): New combine pattern. gcc/testsuite/ * gcc.target/aarch64/sve2/shracc_1.c: New test. From-SVN: r276174
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2019-09-27 Yuliang Wang <yuliang.wang@arm.com>
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* config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>):
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New combine pattern.
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2019-09-26 Max Filippov <jcmvbkbc@gmail.com>
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2019-09-26 Max Filippov <jcmvbkbc@gmail.com>
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* config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
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* config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
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}
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}
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;; Unpredicated signed / unsigned shift-right accumulate.
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(define_insn_and_rewrite "*aarch64_sve2_sra<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(plus:SVE_I
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(unspec:SVE_I
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[(match_operand 4)
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(SHIFTRT:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w")
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(match_operand:SVE_I 3 "aarch64_simd_rshift_imm" "Dr"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_I 1 "register_operand" "0")))]
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"TARGET_SVE2"
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"<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3"
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"&& !CONSTANT_P (operands[4])"
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{
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operands[4] = CONSTM1_RTX (<VPRED>mode);
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}
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)
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2019-09-27 Yuliang Wang <yuliang.wang@arm.com>
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* gcc.target/aarch64/sve2/shracc_1.c: New test.
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2019-09-26 Eric Botcazou <ebotcazou@adacore.com>
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2019-09-26 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.dg/cpp/ucs.c: Add test for new warning and adjust.
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* gcc.dg/cpp/ucs.c: Add test for new warning and adjust.
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details --save-temps" } */
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#include <stdint.h>
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#define SHRACC(TYPE,SHIFT) \
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void __attribute__ ((noinline, noclone)) \
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f_##TYPE##_##SHIFT \
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(TYPE *restrict a, TYPE *restrict b, int n) \
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{ \
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for (int i = 0; i < n; i++) \
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a[i] += b[i] >> (SHIFT); \
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}
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SHRACC (int8_t, 5);
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SHRACC (int16_t, 14);
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SHRACC (int32_t, 19);
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SHRACC (int64_t, 27);
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SHRACC (uint8_t, 2);
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SHRACC (uint16_t, 6);
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SHRACC (uint32_t, 24);
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SHRACC (uint64_t, 53);
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */
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/* { dg-final { scan-assembler-not {\tasr\t} } } */
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/* { dg-final { scan-assembler-not {\tlsr\t} } } */
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/* { dg-final { scan-assembler-not {\tadd\t} } } */
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/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.h, z[0-9]+\.h, #14\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.s, z[0-9]+\.s, #19\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.d, z[0-9]+\.d, #27\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.s, z[0-9]+\.s, #24\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.d, z[0-9]+\.d, #53\n} 1 } } */
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