Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture
This is causing regressions when mixing with user code compiled in ARM mode. 2019-09-20 Christophe Lyon <christophe.lyon@st.com> Revert: 2019-09-10 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only architecture. From-SVN: r276001
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@ -1,3 +1,12 @@
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2019-09-20 Christophe Lyon <christophe.lyon@st.com>
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Revert:
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2019-09-10 Christophe Lyon <christophe.lyon@st.com>
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Mickaël Guêné <mickael.guene@st.com>
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* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
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architecture.
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2019-09-19 Richard Henderson <richard.henderson@linaro.org>
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2019-09-19 Richard Henderson <richard.henderson@linaro.org>
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* config/aarch64/lse-init.c: New file.
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* config/aarch64/lse-init.c: New file.
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@ -199,11 +199,6 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context,
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return _UVRSR_FAILED;
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return _UVRSR_FAILED;
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vrs->core.r[regno] = *(_uw *) valuep;
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vrs->core.r[regno] = *(_uw *) valuep;
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#if defined(__thumb__)
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/* Force LSB bit since we always run thumb code. */
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if (regno == R_PC)
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vrs->core.r[regno] |= 1;
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#endif
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return _UVRSR_OK;
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return _UVRSR_OK;
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case _UVRSC_VFP:
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case _UVRSC_VFP:
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