diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 67ebd1cc49f..28782890513 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2017-06-16  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp.
+	(armv5te, armv5tej): Likewise.
+	(armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise.
+	(armv7): Add options fp and vfpv3-d16.
+	(armv7-a): Add options fp, simd, vfpv3, vfpv3-d16, vfpv3-d16-fp16,
+	vfpv3-fp16, vfpv4, vfpv4-d16, neon, neon-vfpv3, neon-fp16, neon-vfpv4,
+	nofp and nosimd.
+	(armv7ve): Likewise.
+	(armv7-r): Add options fp, fp.sp, idiv, nofp and noidiv.
+	(armv7e-m): Add options fp, fpv5, fp.dp and nofp.
+	(armv8-a): Add nocrypto option.
+	(armv8.1-a, armv8.2-a): Likewise.
+	(armv8-m.main): add options fp, fp.dp and nofp.
+
 2017-06-16  Richard Earnshaw  <rearnsha@arm.com>
 
 	* config/arm/arm-cpus.in (armv8-a): Add options crc, simd crypto and
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index 6ec0d3bc7d3..2a65ec6f119 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -1365,6 +1365,342 @@ static const struct processors all_cores[] =
   {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL}
 };
 
+static const struct cpu_option arch_opttab_armv5e[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv5te[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv5tej[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6j[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6k[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6z[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6kz[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6zk[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv6t2[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv7[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv7_a[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_NEON, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv7ve[] = {
+  {
+    "fp", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_NEON, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv7_r[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "fp.sp", false,
+    { ISA_VFPv3, isa_nobit }
+  },
+  {
+    "idiv", false,
+    { isa_bit_adiv, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "noidiv", true,
+    { isa_bit_adiv, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_option arch_opttab_armv7e_m[] = {
+  {
+    "fp", false,
+    { ISA_VFPv4, isa_nobit }
+  },
+  {
+    "fpv5", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
 static const struct cpu_option arch_opttab_armv8_a[] = {
   {
     "crc", false,
@@ -1382,6 +1718,10 @@ static const struct cpu_option arch_opttab_armv8_a[] = {
     "nofp", true,
     { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit }
   },
+  {
+    "nocrypto", true,
+    { ISA_CRYPTO, isa_nobit }
+  },
   { NULL, false, {isa_nobit}}
 };
 
@@ -1398,6 +1738,10 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = {
     "nofp", true,
     { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit }
   },
+  {
+    "nocrypto", true,
+    { ISA_CRYPTO, isa_nobit }
+  },
   { NULL, false, {isa_nobit}}
 };
 
@@ -1418,6 +1762,10 @@ static const struct cpu_option arch_opttab_armv8_2_a[] = {
     "nofp", true,
     { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit }
   },
+  {
+    "nocrypto", true,
+    { ISA_CRYPTO, isa_nobit }
+  },
   { NULL, false, {isa_nobit}}
 };
 
@@ -1426,6 +1774,18 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = {
     "dsp", false,
     { isa_bit_ARMv7em, isa_nobit }
   },
+  {
+    "fp", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_FPv5, isa_nobit }
+  },
   { NULL, false, {isa_nobit}}
 };
 
@@ -1527,7 +1887,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv5e,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv5e,
     NULL
   },
   {
@@ -1538,7 +1898,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv5te,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv5te,
     NULL
   },
   {
@@ -1549,7 +1909,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv5tej,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv5tej,
     NULL
   },
   {
@@ -1560,7 +1920,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6,
     NULL
   },
   {
@@ -1571,7 +1931,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6j,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6j,
     NULL
   },
   {
@@ -1582,7 +1942,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6k,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6k,
     NULL
   },
   {
@@ -1593,7 +1953,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6z,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6z,
     NULL
   },
   {
@@ -1604,7 +1964,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6kz,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6zk,
     NULL
   },
   {
@@ -1615,7 +1975,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6kz,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6kz,
     NULL
   },
   {
@@ -1626,7 +1986,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv6t2,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv6t2,
     NULL
   },
   {
@@ -1659,7 +2019,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv7,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv7,
     NULL
   },
   {
@@ -1670,7 +2030,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv7a,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv7_a,
     NULL
   },
   {
@@ -1681,7 +2041,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv7ve,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv7ve,
     NULL
   },
   {
@@ -1692,7 +2052,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv7r,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv7_r,
     NULL
   },
   {
@@ -1714,7 +2074,7 @@ static const struct processors all_architectures[] =
       ISA_ARMv7em,
       isa_nobit
     },
-    NULL,
+    arch_opttab_armv7e_m,
     NULL
   },
   {
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 6c9346cc9ad..7a1fede15f3 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -113,6 +113,9 @@ begin arch armv5e
  tune flags CO_PROC
  base 5E
  isa ARMv5e
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv5e
 
 begin arch armv5te
@@ -120,6 +123,9 @@ begin arch armv5te
  tune flags CO_PROC
  base 5TE
  isa ARMv5te
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv5te
 
 begin arch armv5tej
@@ -127,6 +133,9 @@ begin arch armv5tej
  tune flags CO_PROC
  base 5TEJ
  isa ARMv5tej
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv5tej
 
 begin arch armv6
@@ -134,6 +143,9 @@ begin arch armv6
  tune flags CO_PROC
  base 6
  isa ARMv6
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6
 
 begin arch armv6j
@@ -141,6 +153,9 @@ begin arch armv6j
  tune flags CO_PROC
  base 6J
  isa ARMv6j
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6j
 
 begin arch armv6k
@@ -148,6 +163,9 @@ begin arch armv6k
  tune flags CO_PROC
  base 6K
  isa ARMv6k
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6k
 
 begin arch armv6z
@@ -155,6 +173,9 @@ begin arch armv6z
  tune flags CO_PROC
  base 6Z
  isa ARMv6z
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6z
 
 begin arch armv6kz
@@ -162,6 +183,9 @@ begin arch armv6kz
  tune flags CO_PROC
  base 6KZ
  isa ARMv6kz
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6kz
 
 begin arch armv6zk
@@ -169,6 +193,9 @@ begin arch armv6zk
  tune flags CO_PROC
  base 6KZ
  isa ARMv6kz
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6zk
 
 begin arch armv6t2
@@ -176,6 +203,9 @@ begin arch armv6t2
  tune flags CO_PROC
  base 6T2
  isa ARMv6t2
+ option fp add VFPv2 FP_DBL
+ option vfpv2 add VFPv2 FP_DBL
+ option nofp remove VFPv2 FP_DBL
 end arch armv6t2
 
 begin arch armv6-m
@@ -195,6 +225,9 @@ begin arch armv7
  tune flags CO_PROC
  base 7
  isa ARMv7
+# fp => VFPv3-d16 (only useful for the A+R profile subset).
+ option fp add VFPv3 FP_DBL
+ option vfpv3-d16 add VFPv3 FP_DBL
 end arch armv7
 
 begin arch armv7-a
@@ -202,6 +235,21 @@ begin arch armv7-a
  tune flags CO_PROC
  base 7A
  isa ARMv7a
+# fp => VFPv3-d16, simd => neon-vfpv3
+ option fp add VFPv3 FP_DBL
+ option simd add VFPv3 NEON
+ option vfpv3 add VFPv3 FP_D32
+ option vfpv3-d16 add VFPv3 FP_DBL
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv
+ option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv
+ option vfpv4 add VFPv4 FP_D32
+ option vfpv4-d16 add VFPv4 FP_DBL
+ option neon add VFPv3 NEON
+ option neon-vfpv3 add VFPv3 NEON
+ option neon-fp16 add VFPv3 NEON bit_fp16conv
+ option neon-vfpv4 add VFPv4 NEON
+ option nofp remove VFPv4 NEON
+ option nosimd remove NEON
 end arch armv7-a
 
 begin arch armv7ve
@@ -209,6 +257,21 @@ begin arch armv7ve
  tune flags CO_PROC
  base 7A
  isa ARMv7ve
+# fp => VFPv4-d16, simd => neon-vfpv4
+ option fp add VFPv4 FP_DBL
+ option simd add VFPv4 NEON
+ option vfpv3 add VFPv3 FP_D32
+ option vfpv3-d16 add VFPv3 FP_DBL
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv
+ option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv
+ option vfpv4 add VFPv4 FP_D32
+ option vfpv4-d16 add VFPv4 FP_DBL
+ option neon add VFPv3 NEON
+ option neon-vfpv3 add VFPv3 NEON
+ option neon-fp16 add VFPv3 NEON bit_fp16conv
+ option neon-vfpv4 add VFPv4 NEON
+ option nofp remove VFPv4 NEON
+ option nosimd remove NEON
 end arch armv7ve
 
 begin arch armv7-r
@@ -216,6 +279,12 @@ begin arch armv7-r
  tune flags CO_PROC
  base 7R
  isa ARMv7r
+# ARMv7-r uses VFPv3-d16
+ option fp add VFPv3 FP_DBL
+ option fp.sp add VFPv3
+ option idiv add bit_adiv
+ option nofp remove VFPv3 FP_DBL
+ option noidiv remove bit_adiv
 end arch armv7-r
 
 begin arch armv7-m
@@ -223,6 +292,8 @@ begin arch armv7-m
  tune flags CO_PROC
  base 7M
  isa ARMv7m
+# In theory FP is permitted in v7-m, but in practice no implementations exist.
+# leave it out for now.
 end arch armv7-m
 
 begin arch armv7e-m
@@ -230,6 +301,11 @@ begin arch armv7e-m
  tune flags CO_PROC
  base 7EM
  isa ARMv7em
+# fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16
+ option fp add VFPv4
+ option fpv5 add FPv5
+ option fp.dp add FPv5 FP_DBL
+ option nofp remove FPv5 FP_DBL
 end arch armv7e-m
 
 begin arch armv8-a
@@ -241,6 +317,7 @@ begin arch armv8-a
  option simd add FP_ARMv8 NEON
  option crypto add FP_ARMv8 NEON CRYPTO
  option nofp remove FP_ARMv8 NEON CRYPTO
+ option nocrypto remove CRYPTO
 end arch armv8-a
 
 begin arch armv8.1-a
@@ -251,6 +328,7 @@ begin arch armv8.1-a
  option simd add FP_ARMv8 NEON
  option crypto add FP_ARMv8 NEON CRYPTO
  option nofp remove FP_ARMv8 NEON CRYPTO
+ option nocrypto remove CRYPTO
 end arch armv8.1-a
 
 begin arch armv8.2-a
@@ -262,6 +340,7 @@ begin arch armv8.2-a
  option simd add FP_ARMv8 NEON
  option crypto add FP_ARMv8 NEON CRYPTO
  option nofp remove bit_fp16 FP_ARMv8 NEON CRYPTO
+ option nocrypto remove CRYPTO
 end arch armv8.2-a
 
 begin arch armv8-m.base
@@ -276,6 +355,10 @@ begin arch armv8-m.main
  base 8M_MAIN
  isa ARMv8m_main
  option dsp add bit_ARMv7em
+# fp => FPv5-sp-d16; fp.dp => FPv5-d16
+ option fp add FPv5
+ option fp.dp add FPv5 FP_DBL
+ option nofp remove FPv5
 end arch armv8-m.main
 
 begin arch iwmmxt