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[NDS32] Merge movqi and movhi patterns. 

gcc/
	* config/nds32/nds32.md (movqi, movhi): Merge into mov<mode>.

From-SVN: r259071
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Chung-Ju Wu 2018-04-04 09:19:39 +00:00 committed by Chung-Ju Wu
parent 6e9ca9328a
commit 76dc9cb597
2 changed files with 16 additions and 13 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2018-04-04 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.md (movqi, movhi): Merge into mov<mode>.
2018-04-04 Chung-Ju Wu <jasonwucj@gmail.com>
Kito Cheng <kito.cheng@gmail.com>

25
gcc/config/nds32/nds32.md
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@ -83,25 +83,24 @@
;; For QImode and HImode, the immediate value can be fit in imm20s.
;; So there is no need to split rtx for QI and HI patterns.
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
(define_expand "mov<mode>"
[(set (match_operand:QIHI 0 "general_operand" "")
(match_operand:QIHI 1 "general_operand" ""))]
""
{
/* Need to force register if mem <- !reg. */
if (MEM_P (operands[0]) && !REG_P (operands[1]))
operands[1] = force_reg (QImode, operands[1]);
operands[1] = force_reg (<MODE>mode, operands[1]);
if (MEM_P (operands[1]) && optimize > 0)
{
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (reg, operands[1]));
operands[1] = gen_lowpart (<MODE>mode, reg);
}
})
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
{
/* Need to force register if mem <- !reg. */
if (MEM_P (operands[0]) && !REG_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
})
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")