From 76f93d9994a39b1631bea983cfebf3e9a48c4288 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Wed, 10 Dec 2014 19:30:07 +0100 Subject: [PATCH] re PR target/64180 (PowerPC carry bit improvements) PR target/64180 * config/rs6000/darwin.md (macho_low_si): Remove "r" alternative. (macho_low_di): Ditto. * config/rs6000/rs6000.md (*largetoc_low): Ditto. (tocref): Ditto. (elf_low): Ditto. * config/rs6000/spe.md (mov_si_e500_subreg0_elf_low_be): Ditto. (mov_si_e500_subreg0_elf_low_le): Ditto. (mov_si_e500_subreg4_elf_low_be): Ditto. Reformat condition. (mov_si_e500_subreg4_elf_low_le): Ditto. From-SVN: r218590 --- gcc/ChangeLog | 13 +++++++++++++ gcc/config/rs6000/darwin.md | 16 ++++++---------- gcc/config/rs6000/rs6000.md | 18 +++++++----------- gcc/config/rs6000/spe.md | 18 +++++++++--------- 4 files changed, 35 insertions(+), 30 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2d4a8f99d78..ad0ff1ec30c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2014-12-10 Segher Boessenkool + + PR target/64180 + * config/rs6000/darwin.md (macho_low_si): Remove "r" alternative. + (macho_low_di): Ditto. + * config/rs6000/rs6000.md (*largetoc_low): Ditto. + (tocref): Ditto. + (elf_low): Ditto. + * config/rs6000/spe.md (mov_si_e500_subreg0_elf_low_be): Ditto. + (mov_si_e500_subreg0_elf_low_le): Ditto. + (mov_si_e500_subreg4_elf_low_be): Ditto. Reformat condition. + (mov_si_e500_subreg4_elf_low_le): Ditto. + 2014-12-10 Segher Boessenkool PR target/64180 diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 8b816b7a81d..764f847b26c 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -213,22 +213,18 @@ You should have received a copy of the GNU General Public License }) (define_insn "macho_low_si" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_MACHO && ! TARGET_64BIT" - "@ - la %0,lo16(%2)(%1) - addic %0,%1,lo16(%2)") + "la %0,lo16(%2)(%1)") (define_insn "macho_low_di" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_MACHO && TARGET_64BIT" - "@ - la %0,lo16(%2)(%1) - addic %0,%1,lo16(%2)") + "la %0,lo16(%2)(%1)") (define_split [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8fc186f1fe9..989a296eb33 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -10706,13 +10706,11 @@ "addis %0,%1+%3@u(%2)") (define_insn "*largetoc_low" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand:DI 2 "" "")))] "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" - "@ - addi %0,%1,%2@l - addic %0,%1,%2@l") + "addi %0,%1,%2@l") (define_insn "*largetoc_low_aix" [(set (match_operand:P 0 "gpc_reg_operand" "=r") @@ -10722,7 +10720,7 @@ "la %0,%2@l(%1)") (define_insn_and_split "*tocref" - [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") + [(set (match_operand:P 0 "gpc_reg_operand" "=b") (match_operand:P 1 "small_toc_ref" "R"))] "TARGET_TOC" "la %0,%a1" @@ -10741,13 +10739,11 @@ "lis %0,%1@ha") (define_insn "elf_low" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_ELF && ! TARGET_64BIT" - "@ - la %0,%2@l(%1) - addic %0,%1,%K2") + "la %0,%2@l(%1)") ;; Call and call_value insns (define_expand "call" diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 8eec7b71ed3..07c293cae25 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2519,7 +2519,7 @@ (define_insn_and_split "*mov_si_e500_subreg0_elf_low_be" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) @@ -2538,13 +2538,13 @@ (define_insn "*mov_si_e500_subreg0_elf_low_le" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "!WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) || (TARGET_SPE && mode != DFmode && mode != TFmode)) && TARGET_ELF && !TARGET_64BIT)" - "addic %0,%1,%K2") + "addi %0,%1,%K2") ;; ??? Could use evstwwe for memory stores in some cases, depending on ;; the offset. @@ -2592,17 +2592,17 @@ (define_insn "*mov_si_e500_subreg4_elf_low_be" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "WORDS_BIG_ENDIAN - && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) - || (TARGET_SPE && mode != DFmode && mode != TFmode)) - && TARGET_ELF && !TARGET_64BIT)" - "addic %0,%1,%K2") + && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) + || (TARGET_SPE && mode != DFmode && mode != TFmode)) + && TARGET_ELF && !TARGET_64BIT" + "addi %0,%1,%K2") (define_insn_and_split "*mov_si_e500_subreg4_elf_low_le" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "!WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))