mn10300.c (expand_prologue): Rework so that eliminating the frame pointer produces faster/smaller code.
* mn10300/mn10300.c (expand_prologue): Rework so that eliminating
the frame pointer produces faster/smaller code.
(expand_epilogue): Likewise.
(initial_offset): New function for argument pointer and frame pointer
elimination.
* mn10300/mn10300.h (FIRST_PSEUDO_REGISTER): Bump to 10.
(FIXED_REGISTERS): Add argument pointer register, it's a fake fixed
register.
(CALL_USED_REGISTERS, REG_ALLOC_ORDER): Corresponding changes.
(REGNO_REG_CLASS, REG_CLASS_CONTENTS): Likewise.
(REG_OK_FOR_BASE_P, REGISTER_NAMES): Likewise.
(reg_class, REG_CLASS_NAMES): Delete unwanted DATA_OR_SP_REGS class.
(PREFERRED_OUTPUT_RELOAD_CLASS): Define.
(FIRST_PARM_OFFSET): No longer include register save area in
computation.
(STACK_POINTER_REGNUM): Is now register 9.
(ARG_POINTER_REGNUM): Is now register 8.
(FRAME_POINTER_REQUIRED): Refine.
(ELIMINABLE_REGS, INITIAL_ELIMINATION_OFFSET): Define.
(CAN_DEUG_WITHOUT_FP): Define.
* mn10300/mn10300.md (return_internal): Break into two patterns.
* mn10300/mn10300.h (CONST_OK_FOR_LETTER_P): Handle 'M' too.
(REGISTER_MOVE_COST): Fix errors and refine.
* mn10300/mn10300.c (notice_update_cc): SET_ZN_C0 insns leave the
overflow bit in an unuseable state. Rename CC_SET to CC_TST.
* mn10300/mn10300.md (cc attributes): "set" is gone, replaced by
"tst". Update attributes on various insns.
* mn10300/mn10300.md: Improve sign and zero extension instructions.
(ashlsi3): Improve. Handle address registers too.
(add peephole): Combine two consecutive adjustments of a register
into a single adjustment.
From-SVN: r13700
This commit is contained in:
Jeff Law
parent
e9b1360b49
commit
777fbf098d
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@ -213,14 +213,18 @@ expand_prologue ()
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{
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unsigned int size = get_frame_size ();
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/* For simplicity, we just movm all the callee saved registers to
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the stack with one instruction, then set up the frame pointer
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(if needed), and finally allocate the new stack. */
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emit_insn (gen_store_movm ());
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/* And now store all the registers onto the stack with a
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single two byte instruction. */
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if (regs_ever_live[2] || regs_ever_live[3]
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|| regs_ever_live[6] || regs_ever_live[7]
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|| frame_pointer_needed)
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emit_insn (gen_store_movm ());
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/* Now put the frame pointer into the frame pointer register. */
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if (frame_pointer_needed)
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emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
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/* Allocate stack for this frame. */
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if (size)
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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@ -246,8 +250,23 @@ expand_epilogue ()
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size = 0;
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}
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/* Deallocate remaining stack, restore registers and return. And return. */
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emit_jump_insn (gen_return_internal (GEN_INT (size)));
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/* For simplicity, we just movm all the callee saved registers to
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the stack with one instruction.
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?!? Only save registers which are actually used. Reduces
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stack requireents and is faster. */
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if (regs_ever_live[2] || regs_ever_live[3]
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|| regs_ever_live[6] || regs_ever_live[7]
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|| frame_pointer_needed)
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emit_jump_insn (gen_return_internal_regs (GEN_INT (size)));
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else
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{
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if (size)
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emit_insn (gen_addsi3 (stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (size)));
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emit_jump_insn (gen_return_internal ());
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}
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}
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/* Update the condition code from the insn. */
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@ -275,14 +294,13 @@ notice_update_cc (body, insn)
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V is always set to 0. C may or may not be set to 0 but that's ok
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because alter_cond will change tests to use EQ/NE. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_NO_OVERFLOW;
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cc_status.flags |= CC_NO_OVERFLOW | CC_OVERFLOW_UNUSABLE;
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cc_status.value1 = recog_operand[0];
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break;
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case CC_SET:
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case CC_TST:
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/* The insn sets all the condition codes, except v is bogus. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_OVERFLOW_UNUSABLE;
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cc_status.value1 = recog_operand[0];
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break;
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@ -334,27 +352,45 @@ secondary_reload_class (class, mode, in)
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/* We can't directly load sp + const_int into a data register;
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we must use an address register as an intermediate. */
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if (class == DATA_REGS
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if (class != SP_REGS
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&& class != ADDRESS_REGS
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&& class != SP_OR_ADDRESS_REGS
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&& (in == stack_pointer_rtx
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|| (GET_CODE (in) == PLUS
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&& XEXP (in, 0) == stack_pointer_rtx)))
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return ADDRESS_REGS;
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/* Get the true register. */
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if (GET_CODE (in) == REG)
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{
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regno = REGNO (in);
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if (regno >= FIRST_PSEUDO_REGISTER)
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regno = true_regnum (in);
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}
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/* We can't copy directly from a data register into the stack
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pointer. */
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if (class == SP_REGS
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&& GET_CODE (in) == REG
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&& regno < 4)
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&& (XEXP (in, 0) == stack_pointer_rtx
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|| XEXP (in, 1) == stack_pointer_rtx))))
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return ADDRESS_REGS;
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/* Otherwise assume no secondary reloads are needed. */
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return NO_REGS;
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}
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int
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initial_offset (from, to)
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int from, to;
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{
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if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
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{
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if (regs_ever_live[2] || regs_ever_live[3]
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|| regs_ever_live[6] || regs_ever_live[7]
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|| frame_pointer_needed)
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return 20;
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else
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return 4;
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}
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if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
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{
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if (regs_ever_live[2] || regs_ever_live[3]
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|| regs_ever_live[6] || regs_ever_live[7]
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|| frame_pointer_needed)
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return get_frame_size () + 20;
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else
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return get_frame_size () + 4;
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}
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if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
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return get_frame_size ();
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abort ();
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}
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@ -131,13 +131,13 @@ extern int target_flags;
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers. */
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#define FIRST_PSEUDO_REGISTER 9
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#define FIRST_PSEUDO_REGISTER 10
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator. */
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#define FIXED_REGISTERS \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 1}
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{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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@ -148,10 +148,10 @@ extern int target_flags;
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like. */
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#define CALL_USED_REGISTERS \
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{ 1, 1, 0, 0, 1, 1, 0, 0, 1}
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{ 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
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#define REG_ALLOC_ORDER \
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{ 0, 1, 4, 5, 2, 3, 6, 7, 8}
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{ 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
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/* Return number of consecutive hard regs needed starting at reg REGNO
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to hold something of mode MODE.
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@ -202,7 +202,7 @@ extern int target_flags;
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class that represents their union. */
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enum reg_class {
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NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, DATA_OR_SP_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
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NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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@ -211,8 +211,8 @@ enum reg_class {
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
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"SP_REGS", "DATA_OR_ADDRESS_REGS", "DATA_OR_SP_REGS", \
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"SP_OR_ADDRESS_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
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"SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
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"GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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@ -221,13 +221,12 @@ enum reg_class {
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#define REG_CLASS_CONTENTS \
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{ 0, /* No regs */ \
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0x00f, /* DATA_REGS */ \
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0x0f0, /* ADDRESS_REGS */ \
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0x100, /* SP_REGS */ \
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0x0ff, /* DATA_OR_ADDRESS_REGS */\
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0x00f, /* DATA_OR_SP_REGS */ \
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0x0f0, /* SP_OR_ADDRESS_REGS */\
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0x0ff, /* GENERAL_REGS */ \
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0x0ff, /* ALL_REGS */ \
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0x1f0, /* ADDRESS_REGS */ \
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0x200, /* SP_REGS */ \
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0x1ff, /* DATA_OR_ADDRESS_REGS */\
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0x1f0, /* SP_OR_ADDRESS_REGS */\
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0x1ff, /* GENERAL_REGS */ \
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0x3ff, /* ALL_REGS */ \
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}
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/* The same information, inverted:
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@ -237,8 +236,8 @@ enum reg_class {
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) < 4 ? DATA_REGS : \
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(REGNO) < 8 ? ADDRESS_REGS : \
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(REGNO) == 8 ? SP_REGS: 0)
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(REGNO) < 9 ? ADDRESS_REGS : \
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(REGNO) == 9 ? SP_REGS: 0)
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/* The class value for index registers, and the one for base regs. */
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@ -277,6 +276,9 @@ enum reg_class {
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#define PREFERRED_RELOAD_CLASS(X,CLASS) \
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(X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
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#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
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(X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
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#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
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((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
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@ -302,12 +304,14 @@ enum reg_class {
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#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
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#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
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#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
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#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
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(C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
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(C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
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(C) == 'L' ? CONST_OK_FOR_L (VALUE) : 0)
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(C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
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(C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0)
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/* Similar, but for floating constants, and defining letters G and H.
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@ -343,19 +347,21 @@ enum reg_class {
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/* Is equal to the size of the saved fp + pc, even if an fp isn't
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saved since the value is used before we know. */
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#define FIRST_PARM_OFFSET(FNDECL) (-4 + 20)
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#define FIRST_PARM_OFFSET(FNDECL) -4
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM 8
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#define STACK_POINTER_REGNUM 9
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM 7
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 7
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/* Base register for access to arguments of the function. This
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is a fake register and will be eliminated into either the frame
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pointer or stack pointer. */
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#define ARG_POINTER_REGNUM 8
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/* Register in which static-chain is passed to a function. */
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#define STATIC_CHAIN_REGNUM 5
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@ -363,18 +369,40 @@ enum reg_class {
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/* Value should be nonzero if functions must have frame pointers.
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Zero means the frame pointer need not be set up (and parms
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may be accessed via the stack pointer) in functions that seem suitable.
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This is computed in `reload', in reload1.c.
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This is computed in `reload', in reload1.c.
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Currently we always need a frame pointer. In the future we'd like
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to be able to eliminate it. */
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#define FRAME_POINTER_REQUIRED 1
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We allow frame pointers to be eliminated when not having one will
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not interfere with debugging.
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/* Store in the variable DEPTH the initial difference between the
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frame pointer reg contents and the stack pointer reg contents,
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as of the start of the function body. This depends on the layout
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of the fixed parts of the stack frame and on how registers are saved. */
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* If this is a leaf function, then we can keep the stack pointer
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constant throughout the function, and therefore gdb can easily
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find the base of the current frame.
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#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 20
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* If this function never allocates stack space for outgoing
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args (ie calls functions with either no args, or args only
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in registers), then the stack pointer will be constant and
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gdb can easily find the base of the current frame.
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We'd really like to define ACCUMULATE_OUTGOING_ARGS and eliminate
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all frame pointer, but currently we can't.
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We probably also want a -m option to eliminate frame pointer, even
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if the resulting executable can not be debugged. */
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#define ELIMINABLE_REGS \
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{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
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{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
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#define CAN_ELIMINATE(FROM, TO) 1
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#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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OFFSET = initial_offset (FROM, TO)
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#define FRAME_POINTER_REQUIRED \
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!(leaf_function_p () || current_function_outgoing_args_size == 0)
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#define CAN_DEBUG_WITHOUT_FP
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/* A guess for the MN10300. */
|
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#define PROMOTE_PROTOTYPES 1
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|
|
@ -565,7 +593,7 @@ enum reg_class {
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/* Nonzero if X is a hard reg that can be used as a base reg
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or if it is a pseudo reg. */
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#define REG_OK_FOR_BASE_P(X) \
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((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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#else
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/* Nonzero if X is a hard reg that can be used as an index. */
|
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#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
|
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|
|
@ -609,7 +637,7 @@ enum reg_class {
|
|||
{ \
|
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if (GET_CODE (index) == CONST_INT) \
|
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goto ADDR; \
|
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if (GET_CODE (index) == REG \
|
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if (REG_P (index) \
|
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&& REG_OK_FOR_INDEX_P (index)) \
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goto ADDR; \
|
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} \
|
||||
|
|
@ -666,7 +694,7 @@ enum reg_class {
|
|||
default: { int _zxy= const_costs(RTX, CODE); \
|
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if(_zxy) return _zxy; break;}
|
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|
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) 3
|
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) (CLASS1 != CLASS2 ? 4 : 0)
|
||||
|
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/* A crude cut at RTX_COSTS for the MN10300. */
|
||||
|
||||
|
|
@ -808,7 +836,7 @@ do { char dstr[30]; \
|
|||
This sequence is indexed by compiler's hard-register-number (see above). */
|
||||
|
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#define REGISTER_NAMES \
|
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{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "sp" }
|
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{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
|
||||
|
||||
/* Print an instruction operand X on file FILE.
|
||||
look in mn10300.c for details */
|
||||
|
|
@ -913,3 +941,4 @@ extern void expand_epilogue ();
|
|||
extern void notice_update_cc ();
|
||||
extern int call_address_operand ();
|
||||
extern enum reg_class secondary_reload_class ();
|
||||
extern int initial_offset ();
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
;; be known (if it isn't that's ok, we don't need it anyway).
|
||||
;; compare - compare instruction
|
||||
;; clobber - value of cc is unknown
|
||||
(define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
|
||||
(define_attr "cc" "none,none_0hit,tst,set_zn_c0,compare,clobber"
|
||||
(const_string "clobber"))
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
|
|
@ -178,12 +178,12 @@
|
|||
[(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
|
||||
""
|
||||
"cmp 0,%0"
|
||||
[(set_attr "cc" "set_zn_c0")])
|
||||
[(set_attr "cc" "tst")])
|
||||
|
||||
(define_insn "cmpsi"
|
||||
[(set (cc0)
|
||||
(compare:SI (match_operand:SI 0 "register_operand" "da")
|
||||
(match_operand:SI 1 "nonmemory_operand" "dai")))]
|
||||
(match_operand:SI 1 "register_operand" "dai")))]
|
||||
""
|
||||
"cmp %1,%0"
|
||||
[(set_attr "cc" "compare")])
|
||||
|
|
@ -223,7 +223,7 @@
|
|||
inc4 %0
|
||||
add %2,%0
|
||||
add %2,%0"
|
||||
[(set_attr "cc" "set,none_0hit,none_0hit,set,none_0hit")])
|
||||
[(set_attr "cc" "set_zn_c0,none_0hit,none_0hit,set_zn_c0,none_0hit")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; SUBTRACT INSTRUCTIONS
|
||||
|
|
@ -235,7 +235,7 @@
|
|||
(match_operand:SI 2 "register_operand" "dai")))]
|
||||
""
|
||||
"sub %2,%0"
|
||||
[(set_attr "cc" "set")])
|
||||
[(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
(define_expand "negsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
|
|
@ -571,38 +571,48 @@
|
|||
;; EXTEND INSTRUCTIONS
|
||||
;; ----------------------------------------------------------------------
|
||||
|
||||
(define_insn "zero_extendhisi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(define_insn "zero_extendqisi2"
|
||||
[(set (match_operand:SI 0 "general_operand" "=d,d,d")
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "0")))]
|
||||
(match_operand:QI 1 "general_operand" "0,d,m")))]
|
||||
""
|
||||
"exthu %0"
|
||||
"@
|
||||
extbu %0
|
||||
mov %1,%0\;extbu %0
|
||||
movbu %1,%0"
|
||||
[(set_attr "cc" "none_0hit")])
|
||||
|
||||
(define_insn "zero_extendqisi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(define_insn "zero_extendhisi2"
|
||||
[(set (match_operand:SI 0 "general_operand" "=d,d,d")
|
||||
(zero_extend:SI
|
||||
(match_operand:QI 1 "register_operand" "0")))]
|
||||
(match_operand:HI 1 "general_operand" "0,d,m")))]
|
||||
""
|
||||
"extbu %0"
|
||||
"@
|
||||
exthu %0
|
||||
mov %1,%0\;exthu %0
|
||||
movhu %1,%0"
|
||||
[(set_attr "cc" "none_0hit")])
|
||||
|
||||
;;- sign extension instructions
|
||||
|
||||
(define_insn "extendhisi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(define_insn "extendqisi2"
|
||||
[(set (match_operand:SI 0 "general_operand" "=d,d")
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "0")))]
|
||||
(match_operand:QI 1 "general_operand" "0,d")))]
|
||||
""
|
||||
"exth %0"
|
||||
"@
|
||||
extb %0
|
||||
mov %1,%0"
|
||||
[(set_attr "cc" "none_0hit")])
|
||||
|
||||
(define_insn "extendqisi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(define_insn "extendhisi2"
|
||||
[(set (match_operand:SI 0 "general_operand" "=d,d")
|
||||
(sign_extend:SI
|
||||
(match_operand:QI 1 "register_operand" "0")))]
|
||||
(match_operand:HI 1 "general_operand" "0,d")))]
|
||||
""
|
||||
"extb %0"
|
||||
"@
|
||||
exth %0
|
||||
mov %1,%0"
|
||||
[(set_attr "cc" "none_0hit")])
|
||||
|
||||
|
||||
|
|
@ -611,13 +621,19 @@
|
|||
;; ----------------------------------------------------------------------
|
||||
|
||||
(define_insn "ashlsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
||||
[(set (match_operand:SI 0 "register_operand" "=da,d,a,d,a,d,a,d")
|
||||
(ashift:SI
|
||||
(match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:QI 2 "nonmemory_operand" "K,di")))]
|
||||
(match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,0")
|
||||
(match_operand:QI 2 "nonmemory_operand" "J,K,K,M,M,L,L,di")))]
|
||||
""
|
||||
"@
|
||||
add %0,%0
|
||||
asl2 %0
|
||||
add %0,%0\;add %0,%0
|
||||
asl2 %0\;add %0,%0
|
||||
add %0,%0\;add %0,%0\;add %0,%0
|
||||
asl2 %0\;asl2 %0
|
||||
add %0,%0\;add %0,%0\;add %0,%0\;add %0,%0
|
||||
asl %2,%0"
|
||||
[(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
|
|
@ -656,15 +672,15 @@
|
|||
DONE;
|
||||
}")
|
||||
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
"0"
|
||||
(define_insn "return_internal"
|
||||
[(const_int 2)]
|
||||
""
|
||||
"rets"
|
||||
[(set_attr "cc" "clobber")])
|
||||
|
||||
;; This insn restores the callee saved registers and does a return, it
|
||||
;; can also deallocate stack space.
|
||||
(define_insn "return_internal"
|
||||
(define_insn "return_internal_regs"
|
||||
[(const_int 0)
|
||||
(match_operand:SI 0 "const_int_operand" "i")
|
||||
(return)]
|
||||
|
|
@ -677,3 +693,20 @@
|
|||
""
|
||||
"movm [d2,d3,a2,a3],(sp)"
|
||||
[(set_attr "cc" "clobber")])
|
||||
|
||||
;; Try to combine consecutive updates of the stack pointer (or any
|
||||
;; other register for that matter).
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "register_operand" "=dax")
|
||||
(plus:SI (match_dup 0)
|
||||
(match_operand 1 "const_int_operand" "")))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(match_operand 2 "const_int_operand" "")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
|
||||
return \"add %1,%0\";
|
||||
}"
|
||||
[(set_attr "cc" "clobber")])
|
||||
|
|
|
|||
Loading…
Reference in New Issue