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re PR target/49641 (Wrong code for ARMv4T and stmia)

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2011-11-16  Richard Earnshaw  <rearnsha@arm.com>
	    Bernd Schmidt <bernds@coudesourcery.com>
	    Sebastian Huber <sebastian.huber@embedded-brains.de>

	PR target/49641
	* config/arm/arm.c (store_multiple_sequence): Avoid cases where
	the base reg is stored iff compiling for Thumb1.

	* gcc.target/arm/pr49641.c: New test.

Co-Authored-By: Bernd Schmidt <bernds@codesourcery.com>
Co-Authored-By: Sebastian Huber <sebastian.huber@embedded-brains.de>

From-SVN: r181416
This commit is contained in:
Richard Earnshaw 2011-11-16 17:02:44 +00:00 committed by Richard Earnshaw
parent 3b04e1e4c4
commit 77b1138b71
4 changed files with 39 additions and 1 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2011-11-16 Richard Earnshaw <rearnsha@arm.com>
Bernd Schmidt <bernds@coudesourcery.com>
Sebastian Huber <sebastian.huber@embedded-brains.de>
PR target/49641
* config/arm/arm.c (store_multiple_sequence): Avoid cases where
the base reg is stored iff compiling for Thumb1.
2011-11-16 Razya Ladelsky <razya@il.ibm.com>
PR tree-optimization/49960

7
gcc/config/arm/arm.c
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@ -10247,6 +10247,9 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
rtx base_reg_rtx = NULL;
int i, stm_case;
/* Write back of base register is currently only supported for Thumb 1. */
int base_writeback = TARGET_THUMB1;
/* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
easily extended if required. */
gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
@ -10304,7 +10307,9 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
/* If it isn't an integer register, then we can't do this. */
if (unsorted_regs[i] < 0
|| (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
|| (TARGET_THUMB2 && unsorted_regs[i] == base_reg)
/* The effects are unpredictable if the base register is
both updated and stored. */
|| (base_writeback && unsorted_regs[i] == base_reg)
|| (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM)
|| unsorted_regs[i] > 14)
return 0;

7
gcc/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2011-11-16 Richard Earnshaw <rearnsha@arm.com>
Bernd Schmidt <bernds@coudesourcery.com>
Sebastian Huber <sebastian.huber@embedded-brains.de>
PR target/49641
* gcc.target/arm/pr49641.c: New test.
2011-11-16 Razya Ladelsky <razya@il.ibm.com>
PR tree-optimization/49960

18
gcc/testsuite/gcc.target/arm/pr49641.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-mthumb -O2" } */
/* { dg-require-effective-target arm_thumb1_ok } */
/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */
typedef struct {
void *t1, *t2, *t3;
} z;
extern volatile int y;
static inline void foo(z *x) {
x->t1 = &x->t2;
x->t2 = ((void *)0);
x->t3 = &x->t1;
}
extern z v;
void bar (void) {
y = 0;
foo(&v);
}