S/390: Use wfc for scalar vector compares
The z13 vector support used the vector style comparison instructions
also for the scalar compares in vector registers. However, it is much
more convenient to just use the compare scalar instruction for that
purpose. The advantage is that this instruction generates a CC result
as our compares usually do. So this results in quite some code to be
removed from the backend.
Regression tested on s390x.
gcc/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/2964.md: Remove the single element vector compare
instructions which are no longer used.
* config/s390/s390.c (s390_select_ccmode): Remove handling of
vector CCmodes.
(s390_canonicalize_comparison): Remove handling of DFmode
compares.
(s390_expand_vec_compare_scalar): Remove function.
(s390_emit_compare): Don't call s390_expand_vec_compare_scalar.
* config/s390/s390.md ("*vec_cmp<insn_cmp>df_cconly"): Remove
pattern.
("*cmp<mode>_ccs"): Add wfcdb instruction.
gcc/testsuite/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/vector/vec-scalar-cmp-1.c: Adjust for the
comparison instructions used from now on.
From-SVN: r246450
This commit is contained in:
Andreas Krebbel
Andreas Krebbel
parent
b5de6e84a5
commit
77c585ca57
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@ -1,3 +1,17 @@
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2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/2964.md: Remove the single element vector compare
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instructions which are no longer used.
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* config/s390/s390.c (s390_select_ccmode): Remove handling of
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vector CCmodes.
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(s390_canonicalize_comparison): Remove handling of DFmode
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compares.
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(s390_expand_vec_compare_scalar): Remove function.
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(s390_emit_compare): Don't call s390_expand_vec_compare_scalar.
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* config/s390/s390.md ("*vec_cmp<insn_cmp>df_cconly"): Remove
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pattern.
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("*cmp<mode>_ccs"): Add wfcdb instruction.
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2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/s390.md ("mov<mode>_64dfp" DD_DF): Use vleig for loading a
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@ -88,7 +88,7 @@ vsh,vsl,vsq,lxebr,cdtr,fiebr,vupllb,vupllf,vupllh,vmrhb,madbr,vtm,vmrhf,\
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vmrhg,vmrhh,axtr,fiebra,vleb,cxtr,vlef,vleg,vleh,vpkf,vpkg,vpkh,vmlob,vmlof,\
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vmloh,lxdb,ldeb,mdtr,vceqfs,adb,wflndb,lxeb,vn,vo,vchlb,vx,mxtr,vchlf,vchlg,\
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vchlh,vfcedbs,vfcedb,vceqgs,cxbr,msdbr,vcdgb,debr,vceqhs,meeb,lcxbr,vavglb,\
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vavglf,vavglg,vavglh,wfcedbs,vmrlb,vmrlf,vmrlg,vmrlh,wfchedbs,vmxb,tcdb,\
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vavglf,vavglg,vavglh,vmrlb,vmrlf,vmrlg,vmrlh,vmxb,tcdb,\
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vmahh,vsrlb,wcgdb,lcdbr,vistrbs,vrepb,wfmdb,vrepf,vrepg,vreph,ler,wcdlgb,\
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ley,vistrb,vistrf,vistrh,tceb,wfsqdb,sqeb,vsumqf,vsumqg,vesrlb,vfeezbs,\
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maebr,vesrlf,vesrlg,vesrlh,vmeb,vmef,vmeh,meebr,vflcdb,wfmadb,vperm,sxtr,\
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@ -96,7 +96,7 @@ vclzf,vgm,vgmb,vgmf,vgmg,vgmh,tdcxt,vzero,msebr,veslb,veslf,veslg,vfenezb,\
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vfenezf,vfenezh,vistrfs,vchf,vchg,vchh,vmhb,vmhf,vmhh,cdb,veslvb,ledbr,\
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veslvf,veslvg,veslvh,wclgdb,vfmdb,vmnlb,vmnlf,vmnlg,vmnlh,vclzb,vfeezfs,\
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vclzg,vclzh,mdb,vmxlb,vmxlf,vmxlg,vmxlh,ltdtr,vsbcbiq,ceb,wfddb,sebr,vistrhs,\
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lxdtr,lcebr,vab,vaf,vag,vah,ltxtr,vlpf,vlpg,vsegb,vaq,vsegf,vsegh,wfchdbs,\
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lxdtr,lcebr,vab,vaf,vag,vah,ltxtr,vlpf,vlpg,vsegb,vaq,vsegf,vsegh,\
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sdtr,cdbr,vfeezhs,le,wldeb,vfmadb,vchlbs,vacccq,vmaleb,vsel,vmalef,vmaleh,\
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vflndb,mdbr,vmlb,wflpdb,ldetr,vpksfs,vpksf,vpksg,vpksh,sqdb,mxbr,sqdbr,\
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vmaeb,veslh,vmaef,vpklsf,vpklsg,vpklsh,verllb,vchb,ddtr,verllf,verllg,verllh,\
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@ -164,7 +164,7 @@ vsl,vsq,lxebr,cdtr,fiebr,vupllb,vupllf,vupllh,vmrhb,madbr,vtm,vmrhf,vmrhg,\
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vmrhh,axtr,fiebra,vleb,cxtr,vlef,vleg,vleh,vpkf,vpkg,vpkh,vmlob,vmlof,vmloh,\
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lxdb,ldeb,vceqfs,adb,wflndb,lxeb,vn,vo,vchlb,vx,vchlf,vchlg,vchlh,vfcedbs,\
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vfcedb,vceqgs,cxbr,msdbr,vcdgb,vceqhs,meeb,lcxbr,vavglb,vavglf,vavglg,vavglh,\
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wfcedbs,vmrlb,vmrlf,vmrlg,vmrlh,wfchedbs,vmxb,tcdb,vmahh,vsrlb,wcgdb,lcdbr,\
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vmrlb,vmrlf,vmrlg,vmrlh,vmxb,tcdb,vmahh,vsrlb,wcgdb,lcdbr,\
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vistrbs,vrepb,wfmdb,vrepf,vrepg,vreph,ler,wcdlgb,ley,vistrb,vistrf,vistrh,\
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tceb,vsumqf,vsumqg,vesrlb,vfeezbs,maebr,vesrlf,vesrlg,vesrlh,vmeb,vmef,\
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vmeh,meebr,vflcdb,wfmadb,vperm,sxtr,vclzf,vgm,vgmb,vgmf,vgmg,vgmh,tdcxt,\
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@ -172,7 +172,7 @@ vzero,msebr,veslb,veslf,veslg,vfenezb,vfenezf,vfenezh,vistrfs,vchf,vchg,\
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vchh,vmhb,vmhf,vmhh,cdb,veslvb,ledbr,veslvf,veslvg,veslvh,wclgdb,vfmdb,\
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vmnlb,vmnlf,vmnlg,vmnlh,vclzb,vfeezfs,vclzg,vclzh,mdb,vmxlb,vmxlf,vmxlg,\
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vmxlh,ltdtr,vsbcbiq,ceb,sebr,vistrhs,lxdtr,lcebr,vab,vaf,vag,vah,ltxtr,\
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vlpf,vlpg,vsegb,vaq,vsegf,vsegh,wfchdbs,sdtr,cdbr,vfeezhs,le,wldeb,vfmadb,\
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vlpf,vlpg,vsegb,vaq,vsegf,vsegh,sdtr,cdbr,vfeezhs,le,wldeb,vfmadb,\
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vchlbs,vacccq,vmaleb,vsel,vmalef,vmaleh,vflndb,mdbr,vmlb,wflpdb,ldetr,vpksfs,\
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vpksf,vpksg,vpksh,vmaeb,veslh,vmaef,vpklsf,vpklsg,vpklsh,verllb,vchb,verllf,\
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verllg,verllh,wfsdb,maeb,vclgdb,vftcidb,vpksgs,vmxf,vmxg,vmxh,fidbra,vmnb,\
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@ -1402,29 +1402,6 @@ s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
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machine_mode
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s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
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{
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if (TARGET_VX
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&& register_operand (op0, DFmode)
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&& register_operand (op1, DFmode))
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{
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/* LT, LE, UNGT, UNGE require swapping OP0 and OP1. Either
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s390_emit_compare or s390_canonicalize_comparison will take
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care of it. */
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switch (code)
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{
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case EQ:
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case NE:
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return CCVEQmode;
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case GT:
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case UNLE:
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return CCVFHmode;
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case GE:
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case UNLT:
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return CCVFHEmode;
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default:
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;
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}
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}
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switch (code)
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{
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case EQ:
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@ -1703,26 +1680,6 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
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*code = (int)swap_condition ((enum rtx_code)*code);
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}
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/* Using the scalar variants of vector instructions for 64 bit FP
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comparisons might require swapping the operands. */
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if (TARGET_VX
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&& register_operand (*op0, DFmode)
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&& register_operand (*op1, DFmode)
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&& (*code == LT || *code == LE || *code == UNGT || *code == UNGE))
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{
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rtx tmp;
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switch (*code)
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{
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case LT: *code = GT; break;
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case LE: *code = GE; break;
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case UNGT: *code = UNLE; break;
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case UNGE: *code = UNLT; break;
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default: ;
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}
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tmp = *op0; *op0 = *op1; *op1 = tmp;
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}
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/* A comparison result is compared against zero. Replace it with
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the (perhaps inverted) original comparison.
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This probably should be done by simplify_relational_operation. */
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@ -1749,56 +1706,6 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
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}
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}
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/* Helper function for s390_emit_compare. If possible emit a 64 bit
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FP compare using the single element variant of vector instructions.
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Replace CODE with the comparison code to be used in the CC reg
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compare and return the condition code register RTX in CC. */
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static bool
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s390_expand_vec_compare_scalar (enum rtx_code *code, rtx cmp1, rtx cmp2,
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rtx *cc)
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{
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machine_mode cmp_mode;
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bool swap_p = false;
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switch (*code)
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{
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case EQ: cmp_mode = CCVEQmode; break;
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case NE: cmp_mode = CCVEQmode; break;
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case GT: cmp_mode = CCVFHmode; break;
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case GE: cmp_mode = CCVFHEmode; break;
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case UNLE: cmp_mode = CCVFHmode; break;
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case UNLT: cmp_mode = CCVFHEmode; break;
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case LT: cmp_mode = CCVFHmode; *code = GT; swap_p = true; break;
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case LE: cmp_mode = CCVFHEmode; *code = GE; swap_p = true; break;
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case UNGE: cmp_mode = CCVFHmode; *code = UNLE; swap_p = true; break;
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case UNGT: cmp_mode = CCVFHEmode; *code = UNLT; swap_p = true; break;
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default: return false;
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}
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if (swap_p)
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{
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rtx tmp = cmp2;
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cmp2 = cmp1;
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cmp1 = tmp;
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}
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emit_insn (gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (2,
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gen_rtx_SET (gen_rtx_REG (cmp_mode, CC_REGNUM),
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gen_rtx_COMPARE (cmp_mode, cmp1,
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cmp2)),
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gen_rtx_CLOBBER (VOIDmode,
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gen_rtx_SCRATCH (V2DImode)))));
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/* This is the cc reg how it will be used in the cc mode consumer.
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It either needs to be CCVFALL or CCVFANY. However, CC1 will
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never be set by the scalar variants. So it actually doesn't
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matter which one we choose here. */
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*cc = gen_rtx_REG (CCVFALLmode, CC_REGNUM);
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return true;
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}
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/* Emit a compare instruction suitable to implement the comparison
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OP0 CODE OP1. Return the correct condition RTL to be placed in
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@ -1810,14 +1717,7 @@ s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
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machine_mode mode = s390_select_ccmode (code, op0, op1);
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rtx cc;
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if (TARGET_VX
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&& register_operand (op0, DFmode)
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&& register_operand (op1, DFmode)
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&& s390_expand_vec_compare_scalar (&code, op0, op1, &cc))
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{
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/* Work has been done by s390_expand_vec_compare_scalar already. */
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}
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else if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
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if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
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{
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/* Do not output a redundant compare instruction if a
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compare_and_swap pattern already computed the result and the
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@ -1317,28 +1317,20 @@
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})
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; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
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; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcdb
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(define_insn "*cmp<mode>_ccs"
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[(set (reg CC_REGNUM)
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(compare (match_operand:FP 0 "register_operand" "f,f")
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(match_operand:FP 1 "general_operand" "f,R")))]
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(compare (match_operand:FP 0 "register_operand" "f,f,v")
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(match_operand:FP 1 "general_operand" "f,R,v")))]
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"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
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"@
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c<xde><bt>r\t%0,%1
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c<xde>b\t%0,%1"
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[(set_attr "op_type" "RRE,RXE")
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(set_attr "type" "fsimp<mode>")
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(set_attr "enabled" "*,<DSF>")])
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c<xde>b\t%0,%1
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wfcdb\t%0,%1"
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[(set_attr "op_type" "RRE,RXE,VRR")
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(set_attr "cpu_facility" "*,*,vx")
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(set_attr "enabled" "*,<DSF>,<DFDI>")])
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; wfcedbs, wfchdbs, wfchedbs
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(define_insn "*vec_cmp<insn_cmp>df_cconly"
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[(set (reg:VFCMP CC_REGNUM)
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(compare:VFCMP (match_operand:DF 0 "register_operand" "v")
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(match_operand:DF 1 "register_operand" "v")))
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(clobber (match_scratch:V2DI 2 "=v"))]
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"TARGET_VX && TARGET_HARD_FLOAT"
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"wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
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[(set_attr "op_type" "VRR")])
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; Compare and Branch instructions
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@ -1,3 +1,8 @@
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2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* gcc.target/s390/vector/vec-scalar-cmp-1.c: Adjust for the
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comparison instructions used from now on.
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2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* gcc.target/s390/s390.exp (check_effective_target_vector):
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@ -6,48 +6,65 @@
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int
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eq (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a == b;
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}
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/* { dg-final { scan-assembler "eq:\n\twfcedbs\t%v\[0-9\]*,%v0,%v2\n\tlhi\t%r2,1\n\tlochine\t%r2,0" } } */
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/* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochine\t%r2,0" } } */
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int
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ne (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a != b;
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}
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/* { dg-final { scan-assembler "ne:\n\twfcedbs\t%v\[0-9\]*,%v0,%v2\n\tlhi\t%r2,1\n\tlochie\t%r2,0" } } */
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/* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochie\t%r2,0" } } */
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int
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gt (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a > b;
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}
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/* { dg-final { scan-assembler "gt:\n\twfchdbs\t%v\[0-9\]*,%v0,%v2\n\tlhi\t%r2,1\n\tlochine\t%r2,0" } } */
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/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */
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int
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ge (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a >= b;
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}
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/* { dg-final { scan-assembler "ge:\n\twfchedbs\t%v\[0-9\]*,%v0,%v2\n\tlhi\t%r2,1\n\tlochine\t%r2,0" } } */
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/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */
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int
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lt (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a < b;
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}
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/* { dg-final { scan-assembler "lt:\n\twfchdbs\t%v\[0-9\]*,%v2,%v0\n\tlhi\t%r2,1\n\tlochine\t%r2,0" } } */
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/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */
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int
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le (double a, double b)
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{
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asm ("" : : :
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"f0", "f1", "f2", "f3", "f4" , "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
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return a <= b;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "le:\n\twfchedbs\t%v\[0-9\]*,%v2,%v0\n\tlhi\t%r2,1\n\tlochine\t%r2,0" } } */
|
||||
|
||||
/* { dg-final { scan-assembler "le:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */
|
||||
|
|
|
|||
Loading…
Reference in New Issue