predicates.md (rx_minmax_operand): New predicate.
* config/rx/predicates.md (rx_minmax_operand): New predicate. Accepts immediates and a restricted subset of MEMs. * config/rx/rx.md (int_modes): New iterator. (smaxsi3, sminsi3): Delete and replace with... (smax<int_mode>3, smin<int_mode>3): New patterns. (umax<>3_u, umax<>3_ur, umax<>3, umin<>3): New patterns. From-SVN: r179315
This commit is contained in:
Nick Clifton
parent
2996d8c332
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783465f8e3
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@ -1,3 +1,12 @@
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2011-09-28 Nick Clifton <nickc@redhat.com>
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* config/rx/predicates.md (rx_minmax_operand): New predicate.
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Accepts immediates and a restricted subset of MEMs.
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* config/rx/rx.md (int_modes): New iterator.
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(smaxsi3, sminsi3): Delete and replace with...
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(smax<int_mode>3, smin<int_mode>3): New patterns.
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(umax<>3_u, umax<>3_ur, umax<>3, umin<>3): New patterns.
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2011-09-28 Richard Guenther <rguenther@suse.de>
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PR middle-end/50460
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@ -29,7 +38,7 @@
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* output.h (SECTION_EXCLUDE): New macro.
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* varasm.c (default_elf_asm_named_section): Check for
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SECTION_EXCLUDE.
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SECTION_EXCLUDE.
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2011-09-27 Richard Sandiford <rdsandiford@googlemail.com>
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@ -72,6 +72,16 @@
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(match_operand 0 "rx_restricted_mem_operand"))
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)
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;; Check that the operand is suitable as the source operand
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;; for a min/max instruction. This is the same as
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;; rx_source_operand except that CONST_INTs are allowed but
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;; REGs and SUBREGs are not.
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(define_predicate "rx_minmaxex_operand"
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(ior (match_operand 0 "immediate_operand")
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(match_operand 0 "rx_restricted_mem_operand"))
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)
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;; Return true if OP is a store multiple operation. This looks like:
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;;
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;; [(set (SP) (MINUS (SP) (INT)))
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@ -22,6 +22,9 @@
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;; This code iterator is used for sign- and zero- extensions.
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(define_mode_iterator small_int_modes [(HI "") (QI "")])
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;; This code iterator is used for max and min operations.
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(define_mode_iterator int_modes [(SI "") (HI "") (QI "")])
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;; We do not handle DFmode here because it is either
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;; the same as SFmode, or if -m64bit-doubles is active
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;; then all operations on doubles have to be handled by
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@ -1160,28 +1163,109 @@
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(set_attr "timings" "22,44")]
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)
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(define_insn "smaxsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))]
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(define_insn "smax<int_modes:mode>3"
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[(set (match_operand:int_modes 0 "register_operand" "=r,r,r,r,r,r")
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(smax:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:int_modes 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))]
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""
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"max\t%Q2, %0"
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[(set_attr "length" "3,4,5,6,7,6")
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(set_attr "timings" "11,11,11,11,11,33")]
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)
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(define_insn "sminsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))]
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(define_insn "smin<int_modes:mode>3"
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[(set (match_operand:int_modes 0 "register_operand" "=r,r,r,r,r,r")
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(smin:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:int_modes 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))]
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""
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"min\t%Q2, %0"
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[(set_attr "length" "3,4,5,6,7,6")
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(set_attr "timings" "11,11,11,11,11,33")]
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)
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(define_insn "umax<small_int_modes:mode>3_u"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
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(zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
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"r,Sint08,Sint16,Sint24,i,Q"))))]
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""
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"max\t%R2, %0"
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[(set_attr "length" "3,4,5,6,7,6")
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(set_attr "timings" "11,11,11,11,11,33")]
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)
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(define_insn "umin<small_int_modes:mode>3_ur"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(smin:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
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"r,Sint08,Sint16,Sint24,i,Q"))
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(match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
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""
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"min\t%R2, %0"
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[(set_attr "length" "3,4,5,6,7,6")
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(set_attr "timings" "11,11,11,11,11,33")]
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)
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(define_insn "umax<small_int_modes:mode>3_ur"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(smax:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
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"r,Sint08,Sint16,Sint24,i,Q"))
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(match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
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""
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"max\t%R2, %0"
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[(set_attr "length" "3,4,5,6,7,6")
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(set_attr "timings" "11,11,11,11,11,33")]
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)
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(define_expand "umax<small_int_modes:mode>3"
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[(set (match_dup 4)
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(zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
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(set (match_dup 3)
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(smax:SI (match_dup 4)
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(match_operand:small_int_modes 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))
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(set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
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(match_dup 6))
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]
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""
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"operands[3] = gen_reg_rtx (SImode);
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operands[4] = gen_reg_rtx (SImode);
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operands[5] = gen_reg_rtx (SImode);
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operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
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TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
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if (GET_CODE (operands[2]) != CONST_INT)
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{
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emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
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operands[2] = operands[5];
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}
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"
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)
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(define_expand "umin<small_int_modes:mode>3"
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[(set (match_dup 4)
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(zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
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(set (match_dup 3)
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(smin:SI (match_dup 4)
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(match_operand:small_int_modes 2 "rx_source_operand"
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"r,Sint08,Sint16,Sint24,i,Q")))
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(set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
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(match_dup 6))
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]
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""
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"operands[3] = gen_reg_rtx (SImode);
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operands[4] = gen_reg_rtx (SImode);
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operands[5] = gen_reg_rtx (SImode);
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operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
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TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
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if (GET_CODE (operands[2]) != CONST_INT)
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{
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emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
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operands[2] = operands[5];
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}
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"
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)
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
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(mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r")
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