rx.md (movsicc): Allow register to register transfers.
* config/rx/rx.md (movsicc): Allow register to register transfers. (*movsicc): Likewise. (*stcc): Restrict this pattern to EQ and NE compares. (*stcc_reg): New pattern. Works for any comparison but only for register transfers. From-SVN: r177665
This commit is contained in:
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c30f448beb
commit
78926be115
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@ -1,3 +1,12 @@
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2011-08-11 Kazuhiro Inaoka <kazuhiro.inaoka.ud@renesas.com>
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* config/rx/rx.md (movsicc): Allow register to register
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transfers.
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(*movsicc): Likewise.
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(*stcc): Restrict this pattern to EQ and NE compares.
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(*stcc_reg): New pattern. Works for any comparison but only for
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register transfers.
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2011-08-11 Diego Novillo <dnovillo@google.com>
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2011-08-11 Diego Novillo <dnovillo@google.com>
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* tree-streamer-out.c (lto_output_ts_decl_with_vis_tree_pointers):
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* tree-streamer-out.c (lto_output_ts_decl_with_vis_tree_pointers):
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@ -164,7 +173,7 @@
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(process_decls): Use process_bypass. Update after field name changes.
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(process_decls): Use process_bypass. Update after field name changes.
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2011-08-11 Georg-Johann Lay <avr@gjlay.de>
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2011-08-11 Georg-Johann Lay <avr@gjlay.de>
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PR target/49687
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PR target/49687
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* config/avr/avr.md (smulqi3_highpart): New insn.
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* config/avr/avr.md (smulqi3_highpart): New insn.
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(umulqi3_highpart): New insn.
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(umulqi3_highpart): New insn.
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@ -708,24 +708,24 @@
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(clobber (reg:CC CC_REG))])]
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(clobber (reg:CC CC_REG))])]
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""
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""
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{
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{
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/* ??? Support other conditions via cstore into a temporary? */
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/* One operand must be a constant or a register, the other must be a register. */
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if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
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if ( ! CONSTANT_P (operands[2])
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FAIL;
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&& ! CONSTANT_P (operands[3])
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/* One operand must be a constant. */
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&& ! (REG_P (operands[2]) && REG_P (operands[3])))
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if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
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FAIL;
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FAIL;
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})
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})
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(define_insn_and_split "*movsicc"
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(define_insn_and_split "*movsicc"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(if_then_else:SI
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(if_then_else:SI
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(match_operator 5 "rx_z_comparison_operator"
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(match_operator 5 "comparison_operator"
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[(match_operand:SI 3 "register_operand" "r,r")
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[(match_operand:SI 3 "register_operand" "r,r,r")
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(match_operand:SI 4 "rx_source_operand" "riQ,riQ")])
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(match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")])
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(match_operand:SI 1 "nonmemory_operand" "i,ri")
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(match_operand:SI 1 "nonmemory_operand" "i,ri,r")
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(match_operand:SI 2 "nonmemory_operand" "ri,i")))
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(match_operand:SI 2 "nonmemory_operand" "ri,i,r")))
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(clobber (reg:CC CC_REG))]
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(clobber (reg:CC CC_REG))]
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"CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])"
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"(CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))
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|| (REG_P (operands[1]) && REG_P (operands[2]))"
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"#"
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"#"
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"&& reload_completed"
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"&& reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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@ -742,8 +742,11 @@
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op1 = operands[1];
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op1 = operands[1];
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op2 = operands[2];
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op2 = operands[2];
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/* If OP2 is the constant, reverse the sense of the move. */
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/* If OP2 is the constant, reverse the sense of the move.
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if (!CONSTANT_P (operands[1]))
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Likewise if both operands are registers but OP1 == OP0. */
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if ((! CONSTANT_P (operands[1]) && CONSTANT_P (operands[2]))
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|| (REG_P (operands[1]) && REG_P (operands[2])
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&& rtx_equal_p (op0, op1)))
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{
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{
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x = op1, op1 = op2, op2 = x;
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x = op1, op1 = op2, op2 = x;
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cmp_code = reverse_condition (cmp_code);
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cmp_code = reverse_condition (cmp_code);
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@ -752,7 +755,7 @@
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/* If OP2 does not match the output, copy it into place. We have allowed
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/* If OP2 does not match the output, copy it into place. We have allowed
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these alternatives so that the destination can legitimately be one of
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these alternatives so that the destination can legitimately be one of
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the comparison operands without increasing register pressure. */
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the comparison operands without increasing register pressure. */
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if (!rtx_equal_p (op0, op2))
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if (! rtx_equal_p (op0, op2))
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emit_move_insn (op0, op2);
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emit_move_insn (op0, op2);
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x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
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x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
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@ -768,16 +771,33 @@
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[(reg CC_REG) (const_int 0)])
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[(reg CC_REG) (const_int 0)])
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(match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
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(match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
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(match_dup 0)))]
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(match_dup 0)))]
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"reload_completed"
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"reload_completed
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{
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&& ((GET_CODE (operands[2]) == EQ) || (GET_CODE (operands[2]) == NE))"
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if (GET_CODE (operands[2]) == EQ)
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{
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return "stz\t%1, %0";
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if (GET_CODE (operands[2]) == EQ)
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else
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return "stz\t%1, %0";
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return "stnz\t%1, %0";
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else
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}
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return "stnz\t%1, %0";
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}
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[(set_attr "length" "4,5,6,7")]
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[(set_attr "length" "4,5,6,7")]
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)
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)
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(define_insn "*stcc_reg"
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[(set (match_operand:SI 0 "register_operand" "+r,r,r,r,r,r")
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(if_then_else:SI
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(match_operator 2 "comparison_operator"
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[(reg CC_REG) (const_int 0)])
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(match_operand:SI 1 "nonmemory_operand"
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"r,Uint04,Sint08,Sint16,Sint24,i")
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(match_dup 0)))]
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"reload_completed"
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{
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PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
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return "b%B2 1f\n\tmov %1, %0\n1:";
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}
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[(set_attr "length" "3,3,4,5,6,7")]
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)
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;; Arithmetic Instructions
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;; Arithmetic Instructions
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(define_insn "abssi2"
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(define_insn "abssi2"
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