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i386.md (smaxmin): New.

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2008-04-01  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md (smaxmin): New.
	(umaxmin): Likewise.
	(maxminiprefix): Likewise.
	(maxminfprefix): Likewise.
	(<code><mode>3): Likewise.
	(smin<mode>3): Removed.
	(smax<mode>3): Likewise.

	* config/i386/mmx.md (mmx_<code>v2sf3): New.
	(mmx_<code>v4hi3): Likewise.
	(mmx_<code>v8qi3): Likewise.
	(mmx_smaxv2sf3): Removed.
	(mmx_sminv2sf3): Likewise.
	(mmx_umaxv8qi3): Likewise.
	(mmx_smaxv4hi3): Likewise.
	(mmx_uminv8qi3): Likewise.
	(mmx_sminv4hi3): Likewise.

	* config/i386/sse.md (<addsub><mode>3): New.
	(*<addsub><mode>3): Likewise.
	(<sse>_vm<addsub><mode>3): Likewise.
	(<maxmin><mode>3): Likewise.
	(*<maxmin><mode>3_finite): Likewise.
	(*<maxmin><mode>3): Likewise.
	(<sse>_vm<maxmin><mode>3): Likewise.
	(sse3_h<addsub>v4sf3): Likewise.
	(sse3_h<addsub>v2df3): Likewise.
	(<maxmin>v16qi3): Likewise.
	(*<maxmin>v16qi3): Likewise.
	(<maxmin>v8hi3): Likewise.
	(*<maxmin>v8hi3): Likewise.
	(*sse4_1_<maxmin><mode>3): Likewise.
	(*sse4_1_<maxmin><mode>3): Likewise.
	(add<mode>3): Removed.
	(*add<mode>3): Likewise.
	(<sse>_vmadd<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(*sub<mode>3): Likewise.
	(<sse>_vmsub<mode>3): Likewise.
	(smin<mode>3): Likewise.
	(*smin<mode>3_finite): Likewise.
	(*smin<mode>3): Likewise.
	(<sse>_vmsmin<mode>3): Likewise.
	(smax<mode>3): Likewise.
	(*smax<mode>3_finite): Likewise.
	(*smax<mode>3): Likewise.
	(<sse>_vmsmax<mode>3): Likewise.
	(sse3_haddv4sf3): Likewise.
	(sse3_haddv2df3): Likewise.
	(sse3_hsubv4sf3): Likewise.
	(sse3_hsubv2df3): Likewise.
	(umaxv16qi3): Likewise.
	(*umaxv16qi3): Likewise.
	(smaxv8hi3): Likewise.
	(*smaxv8hi3): Likewise.
	(*sse4_1_smax<mode>3): Likewise.
	(*sse4_1_umax<mode>3): Likewise.
	(uminv16qi3): Likewise.
	(*uminv16qi3): Likewise.
	(sminv8hi3): Likewise.
	(*sminv8hi3): Likewise.
	(*sse4_1_smin<mode>3): Likewise.
	(*sse4_1_umin<mode>3): Likewise.

From-SVN: r133797
This commit is contained in:
H.J. Lu 2008-04-01 12:12:31 -07:00
parent 220f1c2948
commit 78e8956be7
4 changed files with 160 additions and 294 deletions
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68
gcc/ChangeLog
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@ -1,7 +1,73 @@
2008-04-01 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.md (smaxmin): New.
(umaxmin): Likewise.
(maxminiprefix): Likewise.
(maxminfprefix): Likewise.
(<code><mode>3): Likewise.
(smin<mode>3): Removed.
(smax<mode>3): Likewise.
* config/i386/mmx.md (mmx_<code>v2sf3): New.
(mmx_<code>v4hi3): Likewise.
(mmx_<code>v8qi3): Likewise.
(mmx_smaxv2sf3): Removed.
(mmx_sminv2sf3): Likewise.
(mmx_umaxv8qi3): Likewise.
(mmx_smaxv4hi3): Likewise.
(mmx_uminv8qi3): Likewise.
(mmx_sminv4hi3): Likewise.
* config/i386/sse.md (<addsub><mode>3): New.
(*<addsub><mode>3): Likewise.
(<sse>_vm<addsub><mode>3): Likewise.
(<maxmin><mode>3): Likewise.
(*<maxmin><mode>3_finite): Likewise.
(*<maxmin><mode>3): Likewise.
(<sse>_vm<maxmin><mode>3): Likewise.
(sse3_h<addsub>v4sf3): Likewise.
(sse3_h<addsub>v2df3): Likewise.
(<maxmin>v16qi3): Likewise.
(*<maxmin>v16qi3): Likewise.
(<maxmin>v8hi3): Likewise.
(*<maxmin>v8hi3): Likewise.
(*sse4_1_<maxmin><mode>3): Likewise.
(*sse4_1_<maxmin><mode>3): Likewise.
(add<mode>3): Removed.
(*add<mode>3): Likewise.
(<sse>_vmadd<mode>3): Likewise.
(sub<mode>3): Likewise.
(*sub<mode>3): Likewise.
(<sse>_vmsub<mode>3): Likewise.
(smin<mode>3): Likewise.
(*smin<mode>3_finite): Likewise.
(*smin<mode>3): Likewise.
(<sse>_vmsmin<mode>3): Likewise.
(smax<mode>3): Likewise.
(*smax<mode>3_finite): Likewise.
(*smax<mode>3): Likewise.
(<sse>_vmsmax<mode>3): Likewise.
(sse3_haddv4sf3): Likewise.
(sse3_haddv2df3): Likewise.
(sse3_hsubv4sf3): Likewise.
(sse3_hsubv2df3): Likewise.
(umaxv16qi3): Likewise.
(*umaxv16qi3): Likewise.
(smaxv8hi3): Likewise.
(*smaxv8hi3): Likewise.
(*sse4_1_smax<mode>3): Likewise.
(*sse4_1_umax<mode>3): Likewise.
(uminv16qi3): Likewise.
(*uminv16qi3): Likewise.
(sminv8hi3): Likewise.
(*sminv8hi3): Likewise.
(*sse4_1_smin<mode>3): Likewise.
(*sse4_1_umin<mode>3): Likewise.
2008-04-01 Rafael Espindola <espindola@google.com> 2008-04-01 Rafael Espindola <espindola@google.com>
* tree-cfg.c (verify_expr): remove in_phi. * tree-cfg.c (verify_expr): remove in_phi.
(verify_stmt): Don't call walk_tree with verify_expr. Use (verify_stmt): Don't call walk_tree with verify_expr. Use
is_gimple_min_invariant instead of is_gimple_val. is_gimple_min_invariant instead of is_gimple_val.
2008-04-01 Joseph Myers <joseph@codesourcery.com> 2008-04-01 Joseph Myers <joseph@codesourcery.com>

26
gcc/config/i386/i386.md
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@ -530,6 +530,16 @@
;; Mark commutative operators as such in constraints. ;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (minus "")]) (define_code_attr comm [(plus "%") (minus "")])
;; Mapping of signed max and min
(define_code_iterator smaxmin [smax smin])
;; Mapping of unsigned max and min
(define_code_iterator umaxmin [umax umin])
;; Base name for integer and FP insn mnemonic
(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])
;; All single word integer modes. ;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")]) (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
@ -19505,23 +19515,13 @@
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
;; are undefined in this condition, we're certain this is correct. ;; are undefined in this condition, we're certain this is correct.
(define_insn "smin<mode>3" (define_insn "<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x") [(set (match_operand:MODEF 0 "register_operand" "=x")
(smin:MODEF (smaxmin:MODEF
(match_operand:MODEF 1 "nonimmediate_operand" "%0") (match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))] (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"mins<ssemodefsuffix>\t{%2, %0|%0, %2}" "<maxminfprefix>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(define_insn "smax<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(smax:MODEF
(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])

56
gcc/config/i386/mmx.md
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@ -248,21 +248,13 @@
[(set_attr "type" "mmxmul") [(set_attr "type" "mmxmul")
(set_attr "mode" "V2SF")]) (set_attr "mode" "V2SF")])
(define_insn "mmx_smaxv2sf3" (define_insn "mmx_<code>v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y") [(set (match_operand:V2SF 0 "register_operand" "=y")
(smax:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") (smaxmin:V2SF
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))] (match_operand:V2SF 1 "nonimmediate_operand" "%0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)" "TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)"
"pfmax\\t{%2, %0|%0, %2}" "pf<maxminfprefix>\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "V2SF")])
(define_insn "mmx_sminv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(smin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW && ix86_binary_operator_ok (SMIN, V2SFmode, operands)"
"pfmin\\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
(set_attr "mode" "V2SF")]) (set_attr "mode" "V2SF")])
@ -715,43 +707,25 @@
[(set_attr "type" "mmxmul") [(set_attr "type" "mmxmul")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "mmx_umaxv8qi3" (define_insn "mmx_<code>v4hi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
(umax:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (UMAX, V8QImode, operands)"
"pmaxub\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
(define_insn "mmx_smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y") [(set (match_operand:V4HI 0 "register_operand" "=y")
(smax:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") (smaxmin:V4HI
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))] (match_operand:V4HI 1 "nonimmediate_operand" "%0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A) "(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (SMAX, V4HImode, operands)" && ix86_binary_operator_ok (SMAX, V4HImode, operands)"
"pmaxsw\t{%2, %0|%0, %2}" "p<maxminiprefix>w\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_insn "mmx_uminv8qi3" (define_insn "mmx_<code>v8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y") [(set (match_operand:V8QI 0 "register_operand" "=y")
(umin:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0") (umaxmin:V8QI
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))] (match_operand:V8QI 1 "nonimmediate_operand" "%0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A) "(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (UMIN, V8QImode, operands)" && ix86_binary_operator_ok (UMIN, V8QImode, operands)"
"pminub\t{%2, %0|%0, %2}" "p<maxminiprefix>b\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
(define_insn "mmx_sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(smin:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"(TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (SMIN, V4HImode, operands)"
"pminsw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd") [(set_attr "type" "mmxadd")
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])

304
gcc/config/i386/sse.md
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@ -358,67 +358,36 @@
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;") "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
(define_expand "add<mode>3" (define_expand "<addsub><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "") [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
(plus:SSEMODEF2P (plusminus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*add<mode>3" (define_insn "*<addsub><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(plus:SSEMODEF2P (plusminus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "<comm>0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (PLUS, <MODE>mode, operands)" && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"addp<ssemodesuffixf2c>\t{%2, %0|%0, %2}" "<addsub>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmadd<mode>3" (define_insn "<sse>_vm<addsub><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P (vec_merge:SSEMODEF2P
(plus:SSEMODEF2P (plusminus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
(match_dup 1) (match_dup 1)
(const_int 1)))] (const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (PLUS, V4SFmode, operands)" && ix86_binary_operator_ok (<CODE>, V4SFmode, operands)"
"adds<ssemodesuffixf2c>\t{%2, %0|%0, %2}" "<addsub>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "sub<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
(minus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);")
(define_insn "*sub<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(minus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"subp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmsub<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P
(minus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
(match_dup 1)
(const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"subs<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")]) (set_attr "mode" "<ssescalarmode>")])
@ -601,98 +570,52 @@
;; isn't really correct, as those rtl operators aren't defined when ;; isn't really correct, as those rtl operators aren't defined when
;; applied to NaNs. Hopefully the optimizers won't get too smart on us. ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
(define_expand "smin<mode>3" (define_expand "<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "") [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
(smin:SSEMODEF2P (smaxmin:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
{ {
if (!flag_finite_math_only) if (!flag_finite_math_only)
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands); ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
}) })
(define_insn "*smin<mode>3_finite" (define_insn "*<code><mode>3_finite"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(smin:SSEMODEF2P (smaxmin:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (SMIN, <MODE>mode, operands)" && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"minp<ssemodesuffixf2c>\t{%2, %0|%0, %2}" "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "*smin<mode>3" (define_insn "*<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(smin:SSEMODEF2P (smaxmin:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"minp<ssemodesuffixf2c>\t{%2, %0|%0, %2}" "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmsmin<mode>3" (define_insn "<sse>_vm<code><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P (vec_merge:SSEMODEF2P
(smin:SSEMODEF2P (smaxmin:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
(match_dup 1) (match_dup 1)
(const_int 1)))] (const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)" "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"mins<ssemodesuffixf2c>\t{%2, %0|%0, %2}" "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sse") [(set_attr "type" "sse")
(set_attr "mode" "<ssescalarmode>")]) (set_attr "mode" "<ssescalarmode>")])
(define_expand "smax<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
(smax:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
{
if (!flag_finite_math_only)
operands[1] = force_reg (<MODE>mode, operands[1]);
ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
})
(define_insn "*smax<mode>3_finite"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(smax:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (SMAX, <MODE>mode, operands)"
"maxp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(define_insn "*smax<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(smax:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"maxp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmsmax<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P
(smax:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
(match_dup 1)
(const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"maxs<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")])
;; These versions of the min/max patterns implement exactly the operations ;; These versions of the min/max patterns implement exactly the operations
;; min = (op1 < op2 ? op1 : op2) ;; min = (op1 < op2 ? op1 : op2)
;; max = (!(op1 < op2) ? op1 : op2) ;; max = (!(op1 < op2) ? op1 : op2)
@ -748,93 +671,48 @@
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
(define_insn "sse3_haddv4sf3" (define_insn "sse3_h<addsub>v4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_concat:V4SF (vec_concat:V4SF
(vec_concat:V2SF (vec_concat:V2SF
(plus:SF (plusminus:SF
(vec_select:SF (vec_select:SF
(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 1 "register_operand" "0")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
(plus:SF (plusminus:SF
(vec_select:SF (match_dup 1) (parallel [(const_int 2)])) (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 3)])))) (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SF (vec_concat:V2SF
(plus:SF (plusminus:SF
(vec_select:SF (vec_select:SF
(match_operand:V4SF 2 "nonimmediate_operand" "xm") (match_operand:V4SF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 1)]))) (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
(plus:SF (plusminus:SF
(vec_select:SF (match_dup 2) (parallel [(const_int 2)])) (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))] (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSE3" "TARGET_SSE3"
"haddps\t{%2, %0|%0, %2}" "h<addsub>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "prefix_rep" "1") (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
(define_insn "sse3_haddv2df3" (define_insn "sse3_h<addsub>v2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x") [(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_concat:V2DF (vec_concat:V2DF
(plus:DF (plusminus:DF
(vec_select:DF (vec_select:DF
(match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 1 "register_operand" "0")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
(plus:DF (plusminus:DF
(vec_select:DF (vec_select:DF
(match_operand:V2DF 2 "nonimmediate_operand" "xm") (match_operand:V2DF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)])) (parallel [(const_int 0)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSE3" "TARGET_SSE3"
"haddpd\t{%2, %0|%0, %2}" "h<addsub>pd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")])
(define_insn "sse3_hsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_concat:V4SF
(vec_concat:V2SF
(minus:SF
(vec_select:SF
(match_operand:V4SF 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
(minus:SF
(vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SF
(minus:SF
(vec_select:SF
(match_operand:V4SF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
(minus:SF
(vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSE3"
"hsubps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse3_hsubv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_concat:V2DF
(minus:DF
(vec_select:DF
(match_operand:V2DF 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
(minus:DF
(vec_select:DF
(match_operand:V2DF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSE3"
"hsubpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
@ -3660,36 +3538,40 @@
operands[1] = gen_lowpart (TImode, operands[1]); operands[1] = gen_lowpart (TImode, operands[1]);
}) })
(define_expand "umaxv16qi3" (define_expand "<code>v16qi3"
[(set (match_operand:V16QI 0 "register_operand" "") [(set (match_operand:V16QI 0 "register_operand" "")
(umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "") (umaxmin:V16QI
(match_operand:V16QI 2 "nonimmediate_operand" "")))] (match_operand:V16QI 1 "nonimmediate_operand" "")
(match_operand:V16QI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (UMAX, V16QImode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
(define_insn "*umaxv16qi3" (define_insn "*<code>v16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x") [(set (match_operand:V16QI 0 "register_operand" "=x")
(umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0") (umaxmin:V16QI
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))] (match_operand:V16QI 1 "nonimmediate_operand" "%0")
"TARGET_SSE2 && ix86_binary_operator_ok (UMAX, V16QImode, operands)" (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"pmaxub\t{%2, %0|%0, %2}" "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
"p<maxminiprefix>b\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1") (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "smaxv8hi3" (define_expand "<code>v8hi3"
[(set (match_operand:V8HI 0 "register_operand" "") [(set (match_operand:V8HI 0 "register_operand" "")
(smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "") (smaxmin:V8HI
(match_operand:V8HI 2 "nonimmediate_operand" "")))] (match_operand:V8HI 1 "nonimmediate_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (SMAX, V8HImode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
(define_insn "*smaxv8hi3" (define_insn "*<code>v8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=x")
(smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0") (smaxmin:V8HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))] (match_operand:V8HI 1 "nonimmediate_operand" "%0")
"TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V8HImode, operands)" (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"pmaxsw\t{%2, %0|%0, %2}" "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
"p<maxminiprefix>w\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1") (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
@ -3738,13 +3620,13 @@
} }
}) })
(define_insn "*sse4_1_smax<mode>3" (define_insn "*sse4_1_<code><mode>3"
[(set (match_operand:SSEMODE14 0 "register_operand" "=x") [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
(smax:SSEMODE14 (smaxmin:SSEMODE14
(match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (SMAX, <MODE>mode, operands)" "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"pmaxs<ssevecsize>\t{%2, %0|%0, %2}" "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
@ -3774,51 +3656,17 @@
} }
}) })
(define_insn "*sse4_1_umax<mode>3" (define_insn "*sse4_1_<code><mode>3"
[(set (match_operand:SSEMODE24 0 "register_operand" "=x") [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
(umax:SSEMODE24 (umaxmin:SSEMODE24
(match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (UMAX, <MODE>mode, operands)" "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"pmaxu<ssevecsize>\t{%2, %0|%0, %2}" "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd") [(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1") (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "uminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "")
(umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "")
(match_operand:V16QI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (UMIN, V16QImode, operands);")
(define_insn "*uminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
(umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (UMIN, V16QImode, operands)"
"pminub\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "")
(smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (SMIN, V8HImode, operands);")
(define_insn "*sminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V8HImode, operands)"
"pminsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "smin<mode>3" (define_expand "smin<mode>3"
[(set (match_operand:SSEMODE14 0 "register_operand" "") [(set (match_operand:SSEMODE14 0 "register_operand" "")
(smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "") (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
@ -3844,17 +3692,6 @@
} }
}) })
(define_insn "*sse4_1_smin<mode>3"
[(set (match_operand:SSEMODE14 0 "register_operand" "=x")
(smin:SSEMODE14
(match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (SMIN, <MODE>mode, operands)"
"pmins<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_expand "umin<mode>3" (define_expand "umin<mode>3"
[(set (match_operand:SSEMODE24 0 "register_operand" "") [(set (match_operand:SSEMODE24 0 "register_operand" "")
(umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "") (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
@ -3880,17 +3717,6 @@
} }
}) })
(define_insn "*sse4_1_umin<mode>3"
[(set (match_operand:SSEMODE24 0 "register_operand" "=x")
(umin:SSEMODE24
(match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (UMIN, <MODE>mode, operands)"
"pminu<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Parallel integral comparisons ;; Parallel integral comparisons