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Alphebetize RISC-V Options section 

2017-02-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * docs/invoke.texi (RISC-V Options): Alphabetize.

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@ -1,3 +1,7 @@
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* docs/invoke.texi (RISC-V Options): Alphabetize.
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* doc/invoke.texi (RISC-V Options): Use two spaces to separate

158
gcc/doc/invoke.texi
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@ -959,6 +959,20 @@ Objective-C and Objective-C++ Dialects}.
@emph{PowerPC Options}
See RS/6000 and PowerPC Options.
@emph{RISC-V Options}
@gccoptlist{-mbranch-cost=@var{N-instruction} @gol
-mmemcpy -mno-memcpy @gol
-mplt -mno-plt @gol
-mabi=@var{ABI-string} @gol
-mfdiv -mno-fdiv @gol
-mdiv -mno-div @gol
-march=@var{ISA-string} @gol
-mtune=@var{processor-string} @gol
-msmall-data-limit=@var{N-bytes} @gol
-msave-restore -mno-save-restore @gol
-mcmodel=@var{code-model} @gol
-mexplicit-relocs -mno-explicit-relocs @gol}
@emph{RL78 Options}
@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol
-mcpu=g10 -mcpu=g13 -mcpu=g14 -mg10 -mg13 -mg14 @gol
@ -1026,20 +1040,6 @@ See RS/6000 and PowerPC Options.
-mstack-protector-guard-offset=@var{offset} @gol
-mlra -mno-lra}
@emph{RISC-V Options}
@gccoptlist{-mbranch-cost=@var{N-instruction} @gol
-mmemcpy -mno-memcpy @gol
-mplt -mno-plt @gol
-mabi=@var{ABI-string} @gol
-mfdiv -mno-fdiv @gol
-mdiv -mno-div @gol
-march=@var{ISA-string} @gol
-mtune=@var{processor-string} @gol
-msmall-data-limit=@var{N-bytes} @gol
-msave-restore -mno-save-restore @gol
-mcmodel=@var{code-model} @gol
-mexplicit-relocs -mno-explicit-relocs @gol}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
-mcpu=@gol
@ -13756,9 +13756,9 @@ platform.
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
* RISC-V Options::
* RL78 Options::
* RS/6000 and PowerPC Options::
* RISC-V Options::
* RX Options::
* S/390 and zSeries Options::
* Score Options::
@ -20831,6 +20831,70 @@ these warnings.
These are listed under @xref{RS/6000 and PowerPC Options}.
@node RISC-V Options
@subsection RISC-V Options
@cindex RISC-V Options
These command-line options are defined for RISC-V targets:
@table @gcctabopt
@item -mbranch-cost=@var{n}
@opindex mbranch-cost
Set the cost of branches to roughly @var{n} instructions.
@item -mmemcpy
@itemx -mno-memcpy
@opindex mmemcpy
Don't optimize block moves.
@item -mplt
@itemx -mno-plt
@opindex plt
When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
@item -mabi=@var{ABI-string}
@opindex mabi
Specify integer and floating-point calling convention. This defaults to the
natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for
RV64G.
@item -mfdiv
@itemx -mno-fdiv
@opindex mfdiv
Use hardware floating-point divide and square root instructions. This requires
the F or D extensions for floating-point registers.
@item -mdiv
@itemx -mno-div
@opindex mdiv
Use hardware instructions for integer division. This requires the M extension.
@item -march=@var{ISA-string}
@opindex march
Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}). ISA strings must be
lower-case. Examples include @samp{rv64i}, @samp{rv32g}, and @samp{rv32imaf}.
@item -mtune=@var{processor-string}
@opindex mtune
Optimize the output for the given processor, specified by microarchitecture
name.
@item -msmall-data-limit=@var{n}
@opindex msmall-data-limit
Put global and static data smaller than @var{n} bytes into a special section
(on some targets).
@item -msave-restore
@itemx -mno-save-restore
@opindex msave-restore
Use smaller but slower prologue and epilogue code.
@item -mcmodel=@var{code-model}
@opindex mcmodel
Specify the code model.
@end table
@node RL78 Options
@subsection RL78 Options
@cindex RL78 Options
@ -22152,70 +22216,6 @@ offset from that base register. The default for those is as specified in the
relevant ABI.
@end table
@node RISC-V Options
@subsection RISC-V Options
@cindex RISC-V Options
These command-line options are defined for RISC-V targets:
@table @gcctabopt
@item -mbranch-cost=@var{n}
@opindex mbranch-cost
Set the cost of branches to roughly @var{n} instructions.
@item -mmemcpy
@itemx -mno-memcpy
@opindex mmemcpy
Don't optimize block moves.
@item -mplt
@itemx -mno-plt
@opindex plt
When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
@item -mabi=@var{ABI-string}
@opindex mabi
Specify integer and floating-point calling convention. This defaults to the
natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for
RV64G.
@item -mfdiv
@itemx -mno-fdiv
@opindex mfdiv
Use hardware floating-point divide and square root instructions. This requires
the F or D extensions for floating-point registers.
@item -mdiv
@itemx -mno-div
@opindex mdiv
Use hardware instructions for integer division. This requires the M extension.
@item -march=@var{ISA-string}
@opindex march
Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}). ISA strings must be
lower-case. Examples include @samp{rv64i}, @samp{rv32g}, and @samp{rv32imaf}.
@item -mtune=@var{processor-string}
@opindex mtune
Optimize the output for the given processor, specified by microarchitecture
name.
@item -msmall-data-limit=@var{n}
@opindex msmall-data-limit
Put global and static data smaller than @var{n} bytes into a special section
(on some targets).
@item -msave-restore
@itemx -mno-save-restore
@opindex msave-restore
Use smaller but slower prologue and epilogue code.
@item -mcmodel=@var{code-model}
@opindex mcmodel
Specify the code model.
@end table
@node RX Options
@subsection RX Options
@cindex RX Options