[AArch64] Emit division using the Newton series
2016-06-13 Evandro Menezes <e.menezes@samsung.com>
Wilco Dijkstra <Wilco.Dijkstra@arm.com>
gcc/
* config/aarch64/aarch64-protos.h
(cpu_approx_modes): Add new member "division".
(aarch64_emit_approx_div): Declare new function.
* config/aarch64/aarch64.c
(generic_approx_modes): New member "division".
(exynosm1_approx_modes): Likewise.
(xgene1_approx_modes): Likewise.
(aarch64_emit_approx_div): Define new function.
* config/aarch64/aarch64.md ("div<mode>3"): New expansion.
* config/aarch64/aarch64-simd.md ("div<mode>3"): Likewise.
* config/aarch64/aarch64.opt (-mlow-precision-div): Add new option.
* doc/invoke.texi (-mlow-precision-div): Describe new option.
From-SVN: r237397
This commit is contained in:
Evandro Menezes
parent
98daafa0b3
commit
79a2bc2dc9
@ -192,6 +192,7 @@ struct cpu_branch_cost
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/* Allowed modes for approximations. */
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struct cpu_approx_modes
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{
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const unsigned int division; /* Division. */
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const unsigned int sqrt; /* Square root. */
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const unsigned int recip_sqrt; /* Reciprocal square root. */
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};
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@ -303,6 +304,7 @@ int aarch64_branch_cost (bool, bool);
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enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
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bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
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bool aarch64_constant_address_p (rtx);
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bool aarch64_emit_approx_div (rtx, rtx, rtx);
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bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
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bool aarch64_expand_movmem (rtx *);
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bool aarch64_float_const_zero_rtx_p (rtx);
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@ -1500,7 +1500,19 @@
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[(set_attr "type" "neon_fp_mul_<Vetype><q>")]
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)
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(define_insn "div<mode>3"
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(define_expand "div<mode>3"
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[(set (match_operand:VDQF 0 "register_operand")
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(div:VDQF (match_operand:VDQF 1 "general_operand")
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(match_operand:VDQF 2 "register_operand")))]
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"TARGET_SIMD"
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{
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if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
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DONE;
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operands[1] = force_reg (<MODE>mode, operands[1]);
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})
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(define_insn "*div<mode>3"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(div:VDQF (match_operand:VDQF 1 "register_operand" "w")
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(match_operand:VDQF 2 "register_operand" "w")))]
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@ -396,6 +396,7 @@ static const struct cpu_branch_cost cortexa57_branch_cost =
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/* Generic approximation modes. */
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static const cpu_approx_modes generic_approx_modes =
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{
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AARCH64_APPROX_NONE, /* division */
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AARCH64_APPROX_NONE, /* sqrt */
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AARCH64_APPROX_NONE /* recip_sqrt */
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};
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@ -403,6 +404,7 @@ static const cpu_approx_modes generic_approx_modes =
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/* Approximation modes for Exynos M1. */
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static const cpu_approx_modes exynosm1_approx_modes =
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{
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AARCH64_APPROX_NONE, /* division */
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AARCH64_APPROX_ALL, /* sqrt */
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AARCH64_APPROX_ALL /* recip_sqrt */
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};
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@ -410,6 +412,7 @@ static const cpu_approx_modes exynosm1_approx_modes =
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/* Approximation modes for X-Gene 1. */
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static const cpu_approx_modes xgene1_approx_modes =
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{
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AARCH64_APPROX_NONE, /* division */
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AARCH64_APPROX_NONE, /* sqrt */
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AARCH64_APPROX_ALL /* recip_sqrt */
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};
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@ -7488,6 +7491,95 @@ aarch64_emit_approx_sqrt (rtx dst, rtx src, bool recp)
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return true;
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}
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typedef rtx (*recpe_type) (rtx, rtx);
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/* Select reciprocal initial estimate insn depending on machine mode. */
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static recpe_type
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get_recpe_type (machine_mode mode)
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{
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switch (mode)
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{
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case SFmode: return (gen_aarch64_frecpesf);
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case V2SFmode: return (gen_aarch64_frecpev2sf);
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case V4SFmode: return (gen_aarch64_frecpev4sf);
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case DFmode: return (gen_aarch64_frecpedf);
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case V2DFmode: return (gen_aarch64_frecpev2df);
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default: gcc_unreachable ();
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}
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}
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typedef rtx (*recps_type) (rtx, rtx, rtx);
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/* Select reciprocal series step insn depending on machine mode. */
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static recps_type
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get_recps_type (machine_mode mode)
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{
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switch (mode)
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{
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case SFmode: return (gen_aarch64_frecpssf);
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case V2SFmode: return (gen_aarch64_frecpsv2sf);
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case V4SFmode: return (gen_aarch64_frecpsv4sf);
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case DFmode: return (gen_aarch64_frecpsdf);
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case V2DFmode: return (gen_aarch64_frecpsv2df);
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default: gcc_unreachable ();
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}
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}
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/* Emit the instruction sequence to compute the approximation for the division
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of NUM by DEN in QUO and return whether the sequence was emitted or not. */
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bool
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aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
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{
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machine_mode mode = GET_MODE (quo);
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bool use_approx_division_p = (flag_mlow_precision_div
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|| (aarch64_tune_params.approx_modes->division
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& AARCH64_APPROX_MODE (mode)));
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if (!flag_finite_math_only
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|| flag_trapping_math
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|| !flag_unsafe_math_optimizations
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|| optimize_function_for_size_p (cfun)
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|| !use_approx_division_p)
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return false;
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/* Estimate the approximate reciprocal. */
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rtx xrcp = gen_reg_rtx (mode);
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emit_insn ((*get_recpe_type (mode)) (xrcp, den));
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/* Iterate over the series twice for SF and thrice for DF. */
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int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
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/* Optionally iterate over the series once less for faster performance,
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while sacrificing the accuracy. */
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if (flag_mlow_precision_div)
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iterations--;
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/* Iterate over the series to calculate the approximate reciprocal. */
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rtx xtmp = gen_reg_rtx (mode);
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while (iterations--)
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{
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emit_insn ((*get_recps_type (mode)) (xtmp, xrcp, den));
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if (iterations > 0)
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emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xtmp));
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}
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if (num != CONST1_RTX (mode))
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{
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/* As the approximate reciprocal of DEN is already calculated, only
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calculate the approximate division when NUM is not 1.0. */
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rtx xnum = force_reg (mode, num);
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emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xnum));
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}
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/* Finalize the approximation. */
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emit_set_insn (quo, gen_rtx_MULT (mode, xrcp, xtmp));
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return true;
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}
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/* Return the number of instructions that can be issued per cycle. */
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static int
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aarch64_sched_issue_rate (void)
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@ -4715,11 +4715,22 @@
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[(set_attr "type" "fmul<s>")]
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)
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(define_insn "div<mode>3"
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(define_expand "div<mode>3"
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[(set (match_operand:GPF 0 "register_operand")
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(div:GPF (match_operand:GPF 1 "general_operand")
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(match_operand:GPF 2 "register_operand")))]
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"TARGET_SIMD"
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{
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if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
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DONE;
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operands[1] = force_reg (<MODE>mode, operands[1]);
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})
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(define_insn "*div<mode>3"
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[(set (match_operand:GPF 0 "register_operand" "=w")
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(div:GPF
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(match_operand:GPF 1 "register_operand" "w")
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(match_operand:GPF 2 "register_operand" "w")))]
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(div:GPF (match_operand:GPF 1 "register_operand" "w")
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(match_operand:GPF 2 "register_operand" "w")))]
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"TARGET_FLOAT"
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"fdiv\\t%<s>0, %<s>1, %<s>2"
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[(set_attr "type" "fdiv<s>")]
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@ -161,3 +161,9 @@ Enable the square root approximation. Enabling this reduces
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precision of square root results to about 16 bits for
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single precision and to 32 bits for double precision.
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If enabled, it implies -mlow-precision-recip-sqrt.
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mlow-precision-div
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Common Var(flag_mlow_precision_div) Optimization
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Enable the division approximation. Enabling this reduces
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precision of division results to about 16 bits for
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single precision and to 32 bits for double precision.
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@ -577,6 +577,7 @@ Objective-C and Objective-C++ Dialects}.
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-mfix-cortex-a53-843419 -mno-fix-cortex-a53-843419 @gol
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-mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt@gol
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-mlow-precision-sqrt -mno-low-precision-sqrt@gol
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-mlow-precision-div -mno-low-precision-div @gol
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-march=@var{name} -mcpu=@var{name} -mtune=@var{name}}
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@emph{Adapteva Epiphany Options}
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@ -13040,6 +13041,16 @@ precision of square root results to about 16 bits for
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single precision and to 32 bits for double precision.
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If enabled, it implies @option{-mlow-precision-recip-sqrt}.
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@item -mlow-precision-div
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@item -mno-low-precision-div
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@opindex -mlow-precision-div
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@opindex -mno-low-precision-div
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Enable or disable the division approximation.
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This option only has an effect if @option{-ffast-math} or
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@option{-funsafe-math-optimizations} is used as well. Enabling this reduces
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precision of division results to about 16 bits for
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single precision and to 32 bits for double precision.
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@item -march=@var{name}
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@opindex march
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Specify the name of the target architecture and, optionally, one or
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