Split-up -march=icelake on -march=icelake-server and -march=icelake-client
Split-up -march=icelake on -march=icelake-server and -march=icelake-client gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (PTA_SKYLAKE): Add SGX. (PTA_ICELAKE): Remove. (PTA_ICELAKE_CLIENT): New. (PTA_ICELAKE_SERVER): New. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type): Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake-client and icelake-server. From-SVN: r258518
This commit is contained in:
Julia Koval
Julia Koval
parent
788949a374
commit
79ab536427
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@ -1,3 +1,22 @@
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2018-03-14 Julia Koval <julia.koval@intel.com>
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* config.gcc (icelake-client, icelake-server): New.
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(icelake): Remove.
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* config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit.
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(initial_ix86_arch_features): Ditto.
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(PTA_SKYLAKE): Add SGX.
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(PTA_ICELAKE): Remove.
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(PTA_ICELAKE_CLIENT): New.
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(PTA_ICELAKE_SERVER): New.
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(ix86_option_override_internal): Split up icelake on icelake client and
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icelake server.
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(get_builtin_code_for_version): Ditto.
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(fold_builtin_cpu): Ditto.
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* config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto.
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* config/i386/i386-c.c (ix86_target_macros_internal): Ditto
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* config/i386/i386.h (processor_type): Ditto.
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* doc/invoke.texi: Ditto.
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2018-03-14 Jakub Jelinek <jakub@redhat.com>
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PR sanitizer/83392
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@ -637,7 +637,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
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bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
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core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
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skylake-avx512 cannonlake icelake x86-64 native"
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skylake-avx512 cannonlake icelake-client icelake-server x86-64 native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -825,9 +825,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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if (arch)
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{
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/* This is unknown family 0x6 CPU. */
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/* Assume Ice Lake Server. */
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if (has_wbnoinvd)
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cpu = "icelake-server";
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/* Assume Ice Lake. */
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if (has_gfni)
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cpu = "icelake";
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else if (has_gfni)
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cpu = "icelake-client";
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/* Assume Cannon Lake. */
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else if (has_avx512vbmi)
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cpu = "cannonlake";
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@ -190,9 +190,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__cannonlake");
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def_or_undef (parse_in, "__cannonlake__");
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break;
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case PROCESSOR_ICELAKE:
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def_or_undef (parse_in, "__icelake");
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def_or_undef (parse_in, "__icelake__");
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case PROCESSOR_ICELAKE_CLIENT:
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def_or_undef (parse_in, "__icelake_client");
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def_or_undef (parse_in, "__icelake_client__");
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break;
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case PROCESSOR_ICELAKE_SERVER:
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def_or_undef (parse_in, "__icelake_server");
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def_or_undef (parse_in, "__icelake_server__");
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break;
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/* use PROCESSOR_max to not set/unset the arch macro. */
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case PROCESSOR_max:
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@ -315,8 +319,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_CANNONLAKE:
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def_or_undef (parse_in, "__tune_cannonlake__");
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break;
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case PROCESSOR_ICELAKE:
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def_or_undef (parse_in, "__tune_icelake__");
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case PROCESSOR_ICELAKE_CLIENT:
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def_or_undef (parse_in, "__tune_icelake_client__");
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break;
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case PROCESSOR_ICELAKE_SERVER:
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def_or_undef (parse_in, "__tune_icelake_server__");
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break;
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case PROCESSOR_LAKEMONT:
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def_or_undef (parse_in, "__tune_lakemont__");
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@ -127,48 +127,49 @@ const struct processor_costs *ix86_tune_cost = NULL;
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const struct processor_costs *ix86_cost = NULL;
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/* Processor feature/optimization bitmasks. */
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#define m_386 (1U<<PROCESSOR_I386)
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#define m_486 (1U<<PROCESSOR_I486)
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#define m_PENT (1U<<PROCESSOR_PENTIUM)
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#define m_LAKEMONT (1U<<PROCESSOR_LAKEMONT)
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#define m_PPRO (1U<<PROCESSOR_PENTIUMPRO)
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#define m_PENT4 (1U<<PROCESSOR_PENTIUM4)
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#define m_NOCONA (1U<<PROCESSOR_NOCONA)
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#define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386)
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#define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486)
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#define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM)
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#define m_LAKEMONT (HOST_WIDE_INT_1U<<PROCESSOR_LAKEMONT)
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#define m_PPRO (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUMPRO)
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#define m_PENT4 (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM4)
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#define m_NOCONA (HOST_WIDE_INT_1U<<PROCESSOR_NOCONA)
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#define m_P4_NOCONA (m_PENT4 | m_NOCONA)
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#define m_CORE2 (1U<<PROCESSOR_CORE2)
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#define m_NEHALEM (1U<<PROCESSOR_NEHALEM)
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#define m_SANDYBRIDGE (1U<<PROCESSOR_SANDYBRIDGE)
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#define m_HASWELL (1U<<PROCESSOR_HASWELL)
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#define m_CORE2 (HOST_WIDE_INT_1U<<PROCESSOR_CORE2)
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#define m_NEHALEM (HOST_WIDE_INT_1U<<PROCESSOR_NEHALEM)
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#define m_SANDYBRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_SANDYBRIDGE)
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#define m_HASWELL (HOST_WIDE_INT_1U<<PROCESSOR_HASWELL)
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#define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
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#define m_BONNELL (1U<<PROCESSOR_BONNELL)
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#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT)
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#define m_KNL (1U<<PROCESSOR_KNL)
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#define m_KNM (1U<<PROCESSOR_KNM)
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#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
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#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
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#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
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#define m_INTEL (1U<<PROCESSOR_INTEL)
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#define m_BONNELL (HOST_WIDE_INT_1U<<PROCESSOR_BONNELL)
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#define m_SILVERMONT (HOST_WIDE_INT_1U<<PROCESSOR_SILVERMONT)
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#define m_KNL (HOST_WIDE_INT_1U<<PROCESSOR_KNL)
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#define m_KNM (HOST_WIDE_INT_1U<<PROCESSOR_KNM)
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#define m_SKYLAKE_AVX512 (HOST_WIDE_INT_1U<<PROCESSOR_SKYLAKE_AVX512)
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#define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE)
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#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
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#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
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#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL)
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#define m_GEODE (1U<<PROCESSOR_GEODE)
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#define m_K6 (1U<<PROCESSOR_K6)
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#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE)
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#define m_K6 (HOST_WIDE_INT_1U<<PROCESSOR_K6)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K8 (1U<<PROCESSOR_K8)
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#define m_ATHLON (1U<<PROCESSOR_ATHLON)
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#define m_K8 (HOST_WIDE_INT_1U<<PROCESSOR_K8)
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#define m_ATHLON (HOST_WIDE_INT_1U<<PROCESSOR_ATHLON)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1U<<PROCESSOR_AMDFAM10)
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#define m_BDVER1 (1U<<PROCESSOR_BDVER1)
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#define m_BDVER2 (1U<<PROCESSOR_BDVER2)
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#define m_BDVER3 (1U<<PROCESSOR_BDVER3)
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#define m_BDVER4 (1U<<PROCESSOR_BDVER4)
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#define m_ZNVER1 (1U<<PROCESSOR_ZNVER1)
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#define m_BTVER1 (1U<<PROCESSOR_BTVER1)
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#define m_BTVER2 (1U<<PROCESSOR_BTVER2)
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#define m_AMDFAM10 (HOST_WIDE_INT_1U<<PROCESSOR_AMDFAM10)
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#define m_BDVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER1)
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#define m_BDVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER2)
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#define m_BDVER3 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER3)
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#define m_BDVER4 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER4)
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#define m_ZNVER1 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER1)
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#define m_BTVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER1)
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#define m_BTVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER2)
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#define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
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#define m_BTVER (m_BTVER1 | m_BTVER2)
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#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \
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| m_ZNVER1)
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#define m_GENERIC (1U<<PROCESSOR_GENERIC)
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#define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
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const char* ix86_tune_feature_names[X86_TUNE_LAST] = {
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#undef DEF_TUNE
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@ -182,7 +183,7 @@ unsigned char ix86_tune_features[X86_TUNE_LAST];
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/* Feature tests against the various tunings used to create ix86_tune_features
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based on the processor mask. */
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static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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static unsigned long long initial_ix86_tune_features[X86_TUNE_LAST] = {
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#undef DEF_TUNE
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#define DEF_TUNE(tune, name, selector) selector,
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#include "x86-tune.def"
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@ -194,7 +195,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
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/* Feature tests against the various architecture variations, used to create
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ix86_arch_features based on the processor mask. */
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static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
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static unsigned long long initial_ix86_arch_features[X86_ARCH_LAST] = {
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/* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
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~(m_386 | m_486 | m_PENT | m_LAKEMONT | m_K6),
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@ -860,7 +861,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{"knm", &slm_cost, 16, 15, 16, 7, 16},
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{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
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{"cannonlake", &skylake_cost, 16, 10, 16, 10, 16},
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{"icelake", &skylake_cost, 16, 10, 16, 10, 16},
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{"icelake-client", &skylake_cost, 16, 10, 16, 10, 16},
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{"icelake-server", &skylake_cost, 16, 10, 16, 10, 16},
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{"intel", &intel_cost, 16, 15, 16, 7, 16},
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{"geode", &geode_cost, 0, 0, 0, 0, 0},
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{"k6", &k6_cost, 32, 7, 32, 7, 32},
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@ -3445,6 +3447,8 @@ ix86_option_override_internal (bool main_args_p,
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const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
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const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
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const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
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const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
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const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
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const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
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| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
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@ -3460,16 +3464,18 @@ ix86_option_override_internal (bool main_args_p,
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const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
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| PTA_RDSEED;
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const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
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| PTA_XSAVEC | PTA_XSAVES;
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| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
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const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
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| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
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| PTA_CLWB;
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const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
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| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
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| PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
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const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI
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const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
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| PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
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| PTA_RDPID;
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| PTA_RDPID | PTA_CLWB;
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const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
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| PTA_WBNOINVD;
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const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
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| PTA_AVX512F | PTA_AVX512CD;
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const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
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@ -3541,7 +3547,10 @@ ix86_option_override_internal (bool main_args_p,
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{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
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PTA_SKYLAKE_AVX512},
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{"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE},
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{"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE},
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{"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
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PTA_ICELAKE_CLIENT},
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{"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
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PTA_ICELAKE_SERVER},
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{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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@ -4150,6 +4159,12 @@ ix86_option_override_internal (bool main_args_p,
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if (((processor_alias_table[i].flags & PTA_RDPID) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
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if (((processor_alias_table[i].flags & PTA_PCONFIG) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PCONFIG))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG;
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if (((processor_alias_table[i].flags & PTA_WBNOINVD) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_WBNOINVD))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD;
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if ((processor_alias_table[i].flags
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& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
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@ -32376,9 +32391,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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break;
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case PROCESSOR_HASWELL:
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case PROCESSOR_SKYLAKE_AVX512:
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if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
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arg_str = "icelake";
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else if (new_target->x_ix86_isa_flags
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if (new_target->x_ix86_isa_flags
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& OPTION_MASK_ISA_AVX512VBMI)
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arg_str = "cannonlake";
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else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
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@ -32391,6 +32404,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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arg_str = "haswell";
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priority = P_PROC_AVX2;
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break;
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case PROCESSOR_ICELAKE_CLIENT:
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arg_str = "icelake-client";
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priority = P_PROC_AVX2;
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break;
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case PROCESSOR_ICELAKE_SERVER:
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arg_str = "icelake-server";
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priority = P_PROC_AVX2;
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break;
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case PROCESSOR_BONNELL:
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arg_str = "bonnell";
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priority = P_PROC_SSSE3;
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@ -33105,7 +33126,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_INTEL_COREI7_SKYLAKE,
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M_INTEL_COREI7_SKYLAKE_AVX512,
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M_INTEL_COREI7_CANNONLAKE,
|
||||
M_INTEL_COREI7_ICELAKE
|
||||
M_INTEL_COREI7_ICELAKE_CLIENT,
|
||||
M_INTEL_COREI7_ICELAKE_SERVER
|
||||
};
|
||||
|
||||
static struct _arch_names_table
|
||||
|
|
@ -33130,7 +33152,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
|
|||
{"skylake", M_INTEL_COREI7_SKYLAKE},
|
||||
{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
|
||||
{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
|
||||
{"icelake", M_INTEL_COREI7_ICELAKE},
|
||||
{"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
|
||||
{"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
|
||||
{"bonnell", M_INTEL_BONNELL},
|
||||
{"silvermont", M_INTEL_SILVERMONT},
|
||||
{"knl", M_INTEL_KNL},
|
||||
|
|
|
|||
|
|
@ -387,7 +387,8 @@ extern const struct processor_costs ix86_size_cost;
|
|||
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
|
||||
#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
|
||||
#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
|
||||
#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
|
||||
#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
|
||||
#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
|
||||
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
|
||||
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
|
||||
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
|
||||
|
|
@ -2268,7 +2269,8 @@ enum processor_type
|
|||
PROCESSOR_KNM,
|
||||
PROCESSOR_SKYLAKE_AVX512,
|
||||
PROCESSOR_CANNONLAKE,
|
||||
PROCESSOR_ICELAKE,
|
||||
PROCESSOR_ICELAKE_CLIENT,
|
||||
PROCESSOR_ICELAKE_SERVER,
|
||||
PROCESSOR_INTEL,
|
||||
PROCESSOR_GEODE,
|
||||
PROCESSOR_K6,
|
||||
|
|
|
|||
|
|
@ -26559,14 +26559,23 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
|
|||
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
|
||||
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
|
||||
|
||||
@item Icelake
|
||||
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
|
||||
@item icelake-client
|
||||
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
|
||||
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
|
||||
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
|
||||
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
|
||||
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
|
||||
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
|
||||
|
||||
@item icelake-server
|
||||
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
|
||||
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
|
||||
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
|
||||
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
|
||||
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
|
||||
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
|
||||
set support.
|
||||
|
||||
@item k6
|
||||
AMD K6 CPU with MMX instruction set support.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2018-03-14 Julia Koval <julia.koval@intel.com>
|
||||
|
||||
* g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake
|
||||
server.
|
||||
* gcc.target/i386/funcspec-56.inc: Ditto.
|
||||
|
||||
2018-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
||||
|
||||
* gcc.target/aarch64/sve/mul_highpart_1_run.c: Restrict to
|
||||
|
|
|
|||
|
|
@ -60,10 +60,14 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
|
|||
return 16;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=icelake"))) foo () {
|
||||
int __attribute__ ((target("arch=icelake-client"))) foo () {
|
||||
return 17;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=icelake-server"))) foo () {
|
||||
return 18;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int val = foo ();
|
||||
|
|
@ -86,8 +90,10 @@ int main ()
|
|||
assert (val == 15);
|
||||
else if (__builtin_cpu_is ("cannonlake"))
|
||||
assert (val == 16);
|
||||
else if (__builtin_cpu_is ("icelake"))
|
||||
else if (__builtin_cpu_is ("icelake-client"))
|
||||
assert (val == 17);
|
||||
else if (__builtin_cpu_is ("icelake-server"))
|
||||
assert (val == 18);
|
||||
else
|
||||
assert (val == 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -145,7 +145,8 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
|
|||
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
|
||||
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
|
||||
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
|
||||
extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
|
||||
extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client")));
|
||||
extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server")));
|
||||
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
|
||||
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
|
||||
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2018-03-14 Julia Koval <julia.koval@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.h (processor_subtypes): Split up icelake on
|
||||
icelake client and icelake server.
|
||||
|
||||
2018-03-06 John David Anglin <danglin@gcc.gnu.org>
|
||||
|
||||
* config/pa/fptr.c (_dl_read_access_allowed): New.
|
||||
|
|
|
|||
|
|
@ -70,7 +70,8 @@ enum processor_subtypes
|
|||
INTEL_COREI7_SKYLAKE,
|
||||
INTEL_COREI7_SKYLAKE_AVX512,
|
||||
INTEL_COREI7_CANNONLAKE,
|
||||
INTEL_COREI7_ICELAKE,
|
||||
INTEL_COREI7_ICELAKE_CLIENT,
|
||||
INTEL_COREI7_ICELAKE_SERVER,
|
||||
CPU_SUBTYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue