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re PR target/6082 (memory model wrong for FreeBSD/sparc64) 

2002-04-08  David S. Miller  <davem@redhat.com>

	PR target/6082
	* config/sparc/freebsd.h (SPARC_DEFAULT_CMODEL): Set to CM_MEDLOW

	Make init_priority work on Sparc when using GNU ld.
	* config/sparc/linux.h, config/sparc/linux64.h,
	config/sparc/netbsd-elf.h, config/sparc/freebsd.h
	(CTORS_SECTION_ASM_OP, DTORS_SECTION_ASM_OP): Undefine.
	* config/sparc/sol2-gld.h: New file to do the same.
	* config.gcc (sparc*-*-solaris2*): If gnu_ld=yes add
	sparc/sol2-gld.h to tm_file.

	PR optimization/4328
	* config/sparc/sparc.h (EXTRA_CONSTRAINT): Add new constraint 'W'.
	* doc/md.texi: Document it.
	* config/sparc/sparc.md (movdi_insn_sp64_novis,
	movdi_insn_sp64_vis, movdf_insn_sp32, movdf_insn_v9only_novis,
	movdf_insn_v9only_vis, movdf_insn_sp64_novis,
	movdf_insn_sp64_vis): Use it as MEM constraing with 'e' registers.
	* config/sparc/sparc.c (mem_min_alignment): Fix comment.

From-SVN: r52031
This commit is contained in:
David S. Miller 2002-04-08 10:20:48 -07:00 committed by David S. Miller
parent 11579f33b9
commit 7a31a340a1
11 changed files with 102 additions and 33 deletions
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22
gcc/ChangeLog
View File

@ -1,3 +1,25 @@
2002-04-08 David S. Miller <davem@redhat.com>
PR target/6082
* config/sparc/freebsd.h (SPARC_DEFAULT_CMODEL): Set to CM_MEDLOW
Make init_priority work on Sparc when using GNU ld.
* config/sparc/linux.h, config/sparc/linux64.h,
config/sparc/netbsd-elf.h, config/sparc/freebsd.h
(CTORS_SECTION_ASM_OP, DTORS_SECTION_ASM_OP): Undefine.
* config/sparc/sol2-gld.h: New file to do the same.
* config.gcc (sparc*-*-solaris2*): If gnu_ld=yes add
sparc/sol2-gld.h to tm_file.
PR optimization/4328
* config/sparc/sparc.h (EXTRA_CONSTRAINT): Add new constraint 'W'.
* doc/md.texi: Document it.
* config/sparc/sparc.md (movdi_insn_sp64_novis,
movdi_insn_sp64_vis, movdf_insn_sp32, movdf_insn_v9only_novis,
movdf_insn_v9only_vis, movdf_insn_sp64_novis,
movdf_insn_sp64_vis): Use it as MEM constraing with 'e' registers.
* config/sparc/sparc.c (mem_min_alignment): Fix comment.
2002-04-08 Andreas Jaeger <aj@suse.de>
* stmt.c (expand_asm_operands): Revert last patch from Richard

7
gcc/config.gcc
View File

@ -3075,7 +3075,7 @@ sparc-*-rtems*|sparc-*-rtemself*)
sparcv9-*-solaris2* | sparc64-*-solaris2*)
if test x$gnu_ld = xyes
then
tm_file="sparc/sol2-sld-64.h sparc/sol2-64.h"
tm_file="sparc/sol2-sld-64.h sparc/sol2-64.h sparc/sol2-gld.h"
else
tm_file=sparc/sol2-sld-64.h
fi
@ -3107,6 +3107,7 @@ sparc-hal-solaris2*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sol2.h sparc/hal.h"
tmake_file="sparc/t-halos sparc/t-sol2 sparc/t-crtfm"
if test x$gnu_ld = xyes; then
tm_file="${tm_file} sparc/sol2-gld.h"
tmake_file="$tmake_file t-slibgcc-elf-ver"
else
tmake_file="$tmake_file t-slibgcc-sld"
@ -3125,7 +3126,7 @@ sparc-hal-solaris2*)
sparc-*-solaris2*)
if test x$gnu_ld = xyes
then
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sol2.h"
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sol2.h sparc/sol2-gld.h"
else
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sol2.h sparc/sol2-sld.h"
fi
@ -3142,7 +3143,7 @@ sparc-*-solaris2*)
*-*-solaris2*)
if test x$gnu_ld = xyes
then
tm_file="sparc/sol2-sld-64.h sparc/sol2-64.h"
tm_file="sparc/sol2-sld-64.h sparc/sol2-64.h sparc/sol2-gld.h"
else
tm_file="sparc/sol2-sld-64.h"
fi

6
gcc/config/sparc/freebsd.h
View File

@ -97,7 +97,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* The default code model. */
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDMID
#define SPARC_DEFAULT_CMODEL CM_MEDLOW
/************************[ Assembler stuff ]********************************/
@ -153,3 +153,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#define ENDFILE_SPEC \
"%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" \
FBSD_ENDFILE_SPEC
/* We use GNU ld so undefine this so that attribute((init_priority)) works. */
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP

6
gcc/config/sparc/linux.h
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@ -187,7 +187,7 @@ Boston, MA 02111-1307, USA. */
#undef ASM_SPEC
#define ASM_SPEC \
"%{V} %{v:%{!V:-V}} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} \
%{fPIC:-K PIC} %(asm_relax)"
%{fPIC:-K PIC} %(asm_cpu) %(asm_relax)"
/* Same as sparc.h */
#undef DBX_REGISTER_NUMBER
@ -253,3 +253,7 @@ do { \
/* Don't be different from other Linux platforms in this regard. */
#define HANDLE_PRAGMA_PACK_PUSH_POP
/* We use GNU ld so undefine this so that attribute((init_priority)) works. */
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP

10
gcc/config/sparc/linux64.h
View File

@ -60,8 +60,8 @@ Boston, MA 02111-1307, USA. */
#define STARTFILE_SPEC32 \
"%{!shared: \
%{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
crti.o%s %{static:crtbeginT.o%s}\
%{pg:/usr/lib/gcrt1.o%s} %{!pg:%{/usr/lib/p:gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\
/usr/lib/crti.o%s %{static:crtbeginT.o%s}\
%{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}"
#define STARTFILE_SPEC64 \
@ -99,7 +99,7 @@ Boston, MA 02111-1307, USA. */
#undef ENDFILE_SPEC
#define ENDFILE_SPEC32 \
"%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
"%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib/crtn.o%s"
#define ENDFILE_SPEC64 \
"%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s"
@ -371,3 +371,7 @@ do { \
/* Don't be different from other Linux platforms in this regard. */
#define HANDLE_PRAGMA_PACK_PUSH_POP
/* We use GNU ld so undefine this so that attribute((init_priority)) works. */
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP

4
gcc/config/sparc/netbsd-elf.h
View File

@ -336,3 +336,7 @@ Boston, MA 02111-1307, USA. */
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc */
#endif /* SPARC_BI_ARCH */
/* We use GNU ld so undefine this so that attribute((init_priority)) works. */
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP

6
gcc/config/sparc/sol2-gld.h Normal file
View File

@ -0,0 +1,6 @@
/* Definitions of target machine for GNU compiler, for SPARC running Solaris 2
using the GNU linker. */
/* Undefine this so that attribute((init_priority)) works. */
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP

24
gcc/config/sparc/sparc.c
View File

@ -2989,7 +2989,7 @@ load_pic_register ()
}
/* Return 1 if RTX is a MEM which is known to be aligned to at
least an 8 byte boundary. */
least a DESIRED byte boundary. */
int
mem_min_alignment (mem, desired)
@ -3702,12 +3702,22 @@ sparc_nonflat_function_epilogue (file, size, leaf_function)
if (current_function_epilogue_delay_list == 0)
{
/* If code does not drop into the epilogue, we need
do nothing except output pending case vectors. */
rtx insn = get_last_insn ();
if (GET_CODE (insn) == NOTE)
insn = prev_nonnote_insn (insn);
if (insn && GET_CODE (insn) == BARRIER)
goto output_vectors;
do nothing except output pending case vectors.
We have to still output a dummy nop for the sake of
sane backtraces. Otherwise, if the last two instructions
of a function were call foo; dslot; this can make the return
PC of foo (ie. address of call instruction plus 8) point to
the first instruction in the next function. */
rtx insn;
fputs("\tnop\n", file);
insn = get_last_insn ();
if (GET_CODE (insn) == NOTE)
insn = prev_nonnote_insn (insn);
if (insn && GET_CODE (insn) == BARRIER)
goto output_vectors;
}
if (num_gfregs)

19
gcc/config/sparc/sparc.h
View File

@ -2099,7 +2099,10 @@ do { \
be at least 8 bytes.
`U' handles all pseudo registers or a hard even numbered
integer register, needed for ldd/std instructions. */
integer register, needed for ldd/std instructions.
'W' handles the memory operand when moving operands in/out
of 'e' constraint floating point registers. */
#define EXTRA_CONSTRAINT_BASE(OP, C) \
((C) == 'Q' ? fp_sethi_p(OP) \
@ -2120,7 +2123,8 @@ do { \
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
/* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
/* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
'W' is like 'T' but is assumed true on arch64. */
#define EXTRA_CONSTRAINT(OP, C) \
(EXTRA_CONSTRAINT_BASE(OP, C) \
@ -2128,7 +2132,10 @@ do { \
? (mem_min_alignment (OP, 8)) \
: ((! TARGET_ARCH64 && (C) == 'U') \
? (register_ok_for_ldd (OP)) \
: 0)))
: ((C) == 'W' \
? ((TARGET_ARCH64 && GET_CODE (OP) == MEM) \
|| mem_min_alignment (OP, 8)) \
: 0))))
#else
@ -2146,7 +2153,11 @@ do { \
&& (REGNO (OP) < FIRST_PSEUDO_REGISTER \
|| reg_renumber[REGNO (OP)] >= 0) \
&& register_ok_for_ldd (OP)) \
: 0)))
: ((C) == 'W' \
? (((TARGET_ARCH64 && GET_CODE (OP) == MEM) \
|| mem_min_alignment (OP, 8)) \
&& strict_memory_address_p (Pmode, XEXP (OP, 0))) \
: 0))))
#endif

28
gcc/config/sparc/sparc.md
View File

@ -2592,8 +2592,8 @@
"sethi\\t%%hi(%a1), %0")
(define_insn "*movdi_insn_sp64_novis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,m,e"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e"))]
"TARGET_ARCH64 && ! TARGET_VIS
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
@ -2610,8 +2610,8 @@
(set_attr "fptype" "*,*,*,*,*,double,*,*")])
(define_insn "*movdi_insn_sp64_vis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,m,e,J"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e,J"))]
"TARGET_ARCH64 && TARGET_VIS &&
(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
@ -3272,8 +3272,8 @@
;; Be careful, fmovd does not exist when !v9.
(define_insn "*movdf_insn_sp32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,T,U,T,o,e,*r,o,e,o")
(match_operand:DF 1 "input_operand" "T#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
(match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
"TARGET_FPU
&& ! TARGET_V9
&& (register_operand (operands[0], DFmode)
@ -3332,8 +3332,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS.
(define_insn "*movdf_insn_v9only_novis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,T,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "e,T#F,G,e,T,U,o#F,*roF,*rGe"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGe"))]
"TARGET_FPU
&& TARGET_V9
&& ! TARGET_VIS
@ -3358,8 +3358,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
(define_insn "*movdf_insn_v9only_vis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,T,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "G,e,T#F,G,e,T,U,o#F,*roGF,*rGe"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,e,*r,o")
(match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGe"))]
"TARGET_FPU
&& TARGET_VIS
&& ! TARGET_ARCH64
@ -3384,8 +3384,8 @@
;; We have available both v9 double floats and 64-bit
;; integer registers. No VIS though.
(define_insn "*movdf_insn_sp64_novis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,m,*r,*r,m,*r")
(match_operand:DF 1 "input_operand" "e,m#F,e,*rG,m,*rG,F"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r")
(match_operand:DF 1 "input_operand" "e,W#F,e,*rG,m,*rG,F"))]
"TARGET_FPU
&& ! TARGET_VIS
&& TARGET_ARCH64
@ -3407,8 +3407,8 @@
;; We have available both v9 double floats and 64-bit
;; integer registers. And we have VIS.
(define_insn "*movdf_insn_sp64_vis"
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,m,*r,*r,m,*r")
(match_operand:DF 1 "input_operand" "G,e,m#F,e,*rG,m,*rG,F"))]
[(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
(match_operand:DF 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))]
"TARGET_FPU
&& TARGET_VIS
&& TARGET_ARCH64

3
gcc/doc/md.texi
View File

@ -1897,6 +1897,9 @@ Memory address aligned to an 8-byte boundary
@item U
Even register
@item W
Memory address for @samp{e} constraint registers.
@end table
@item TMS320C3x/C4x---@file{c4x.h}