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aarch64: Fix {ash[lr],lshr}<mode>3 expanders [PR94488] 

The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port.  The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases.  All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR target/94488
	* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
	ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
	Assume it is a REG after that instead of testing it and doing FAIL
	otherwise.  Formatting fix.

	* gcc.c-torture/compile/pr94488.c: New test.
This commit is contained in:
Jakub Jelinek 2020-04-07 10:01:16 +02:00
parent 30d26118f9
commit 7a6588fe65
2 changed files with 53 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
gcc/config/aarch64/aarch64-simd.md
View File

@ -1105,31 +1105,17 @@
tmp));
DONE;
}
else
{
operands[2] = force_reg (SImode, operands[2]);
}
}
else if (MEM_P (operands[2]))
{
operands[2] = force_reg (SImode, operands[2]);
}
if (REG_P (operands[2]))
{
rtx tmp = gen_reg_rtx (<MODE>mode);
emit_insn (gen_aarch64_simd_dup<mode> (tmp,
convert_to_mode (<VEL>mode,
operands[2],
0)));
emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
tmp));
DONE;
}
else
FAIL;
}
)
operands[2] = force_reg (SImode, operands[2]);
rtx tmp = gen_reg_rtx (<MODE>mode);
emit_insn (gen_aarch64_simd_dup<mode> (tmp, convert_to_mode (<VEL>mode,
operands[2],
0)));
emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1], tmp));
DONE;
})
(define_expand "lshr<mode>3"
[(match_operand:VDQ_I 0 "register_operand")
@ -1152,31 +1138,19 @@
tmp));
DONE;
}
else
operands[2] = force_reg (SImode, operands[2]);
}
else if (MEM_P (operands[2]))
{
operands[2] = force_reg (SImode, operands[2]);
}
if (REG_P (operands[2]))
{
rtx tmp = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_negsi2 (tmp, operands[2]));
emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
convert_to_mode (<VEL>mode,
tmp, 0)));
emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0],
operands[1],
tmp1));
DONE;
}
else
FAIL;
}
)
operands[2] = force_reg (SImode, operands[2]);
rtx tmp = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_negsi2 (tmp, operands[2]));
emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
convert_to_mode (<VEL>mode, tmp, 0)));
emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0], operands[1],
tmp1));
DONE;
})
(define_expand "ashr<mode>3"
[(match_operand:VDQ_I 0 "register_operand")
@ -1199,31 +1173,19 @@
tmp));
DONE;
}
else
operands[2] = force_reg (SImode, operands[2]);
}
else if (MEM_P (operands[2]))
{
operands[2] = force_reg (SImode, operands[2]);
}
if (REG_P (operands[2]))
{
rtx tmp = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_negsi2 (tmp, operands[2]));
emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
convert_to_mode (<VEL>mode,
tmp, 0)));
emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0],
operands[1],
tmp1));
DONE;
}
else
FAIL;
}
)
operands[2] = force_reg (SImode, operands[2]);
rtx tmp = gen_reg_rtx (SImode);
rtx tmp1 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_negsi2 (tmp, operands[2]));
emit_insn (gen_aarch64_simd_dup<mode> (tmp1, convert_to_mode (<VEL>mode,
tmp, 0)));
emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0], operands[1],
tmp1));
DONE;
})
(define_expand "vashl<mode>3"
[(match_operand:VDQ_I 0 "register_operand")

22
gcc/testsuite/gcc.c-torture/compile/pr94488.c Normal file
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@ -0,0 +1,22 @@
/* PR target/94488 */
typedef unsigned long V __attribute__((__vector_size__(16)));
typedef long W __attribute__((__vector_size__(16)));
void
foo (V *x, unsigned long y)
{
*x = *x >> (unsigned int) y;
}
void
bar (V *x, unsigned long y)
{
*x = *x << (unsigned int) y;
}
void
baz (W *x, unsigned long y)
{
*x = *x >> (unsigned int) y;
}