sparc.c (gen_df_reg): New function.
* config/sparc/sparc.c (gen_df_reg): New function. * config/sparc/sparc-protos.h (gen_df_reg): Add prototype. * config/sparc/sparc.md (movtf_no_e_insn_sp64+1, movtf_no_e_insn_sp64+2, movtf_no_e_insn_sp64+3, movtf_cc_sp64+1, movtf_cc_reg_sp64+1): Use it. From-SVN: r31177
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3fda1f48b5
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7b1ac7981e
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@ -1,3 +1,11 @@
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2000-01-03 Jakub Jelinek <jakub@redhat.com>
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* config/sparc/sparc.c (gen_df_reg): New function.
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* config/sparc/sparc-protos.h (gen_df_reg): Add prototype.
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* config/sparc/sparc.md (movtf_no_e_insn_sp64+1,
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movtf_no_e_insn_sp64+2, movtf_no_e_insn_sp64+3, movtf_cc_sp64+1,
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movtf_cc_reg_sp64+1): Use it.
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2000-01-02 Mark Mitchell <mark@codesourcery.com>
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* integrate.c (copy_decl_for_inlining): Clear TREE_ADDRESSABLE on
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@ -162,6 +162,7 @@ extern int eq_or_neq PARAMS ((rtx, enum machine_mode));
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extern int normal_comp_operator PARAMS ((rtx, enum machine_mode));
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extern int uns_arith_operand PARAMS ((rtx, enum machine_mode));
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extern int clobbered_register PARAMS ((rtx, enum machine_mode));
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extern rtx gen_df_reg PARAMS ((rtx, int));
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#endif /* RTX_CODE */
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#endif /* __SPARC_PROTOS_H__ */
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@ -2264,6 +2264,22 @@ emit_v9_brxx_insn (code, op0, label)
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gen_rtx_LABEL_REF (VOIDmode, label),
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pc_rtx)));
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}
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/* Generate a DFmode part of a hard TFmode register.
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REG is the TFmode hard register, LOW is 1 for the
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low 64bit of the register and 0 otherwise.
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*/
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rtx
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gen_df_reg (reg, low)
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rtx reg;
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int low;
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{
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int regno = REGNO (reg);
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if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
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regno += (regno < 32) ? 1 : 2;
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return gen_rtx_REG (DFmode, regno);
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}
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/* Return nonzero if a return peephole merging return with
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setting of output register is ok. */
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@ -3643,14 +3643,10 @@
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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dest1 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
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dest2 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
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src1 = gen_rtx_REG (DFmode,
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REGNO (set_src) + (WORDS_BIG_ENDIAN ? 0 : 2));
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src2 = gen_rtx_REG (DFmode,
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REGNO (set_src) + (WORDS_BIG_ENDIAN ? 2 : 0));
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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src1 = gen_df_reg (set_src, 0);
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src2 = gen_df_reg (set_src, 1);
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/* Now emit using the real source and destination we found, swapping
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the order if we detect overlap. */
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@ -3684,10 +3680,8 @@
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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dest1 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
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dest2 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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/* Now output, ordering such that we don't clobber any registers
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mentioned in the address. */
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@ -3716,18 +3710,14 @@
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rtx word1 = change_address (operands[0], DFmode, NULL_RTX);
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rtx word2 = change_address (operands[0], DFmode,
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plus_constant_for_output (XEXP (word1, 0), 8));
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rtx set_src, src1, src2;
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rtx set_src;
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set_src = operands[1];
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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src1 = gen_rtx_REG (DFmode,
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REGNO (set_src) + (WORDS_BIG_ENDIAN ? 0 : 2));
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src2 = gen_rtx_REG (DFmode,
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REGNO (set_src) + (WORDS_BIG_ENDIAN ? 2 : 0));
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emit_insn (gen_movdf (word1, src1));
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emit_insn (gen_movdf (word2, src2));
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emit_insn (gen_movdf (word1, gen_df_reg (set_src, 0)));
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emit_insn (gen_movdf (word2, gen_df_reg (set_src, 1)));
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DONE;
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}")
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@ -4095,18 +4085,12 @@
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if (GET_CODE (set_srcb) == SUBREG)
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set_srcb = alter_subreg (set_srcb);
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dest1 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
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dest2 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
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srca1 = gen_rtx_REG (DFmode,
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REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 0 : 2));
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srca2 = gen_rtx_REG (DFmode,
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REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 2 : 0));
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srcb1 = gen_rtx_REG (DFmode,
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REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 0 : 2));
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srcb2 = gen_rtx_REG (DFmode,
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REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 2 : 0));
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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srca1 = gen_df_reg (set_srca, 0);
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srca2 = gen_df_reg (set_srca, 1);
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srcb1 = gen_df_reg (set_srcb, 0);
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srcb2 = gen_df_reg (set_srcb, 1);
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/* Now emit using the real source and destination we found, swapping
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the order if we detect overlap. */
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@ -4274,18 +4258,12 @@
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if (GET_CODE (set_srcb) == SUBREG)
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set_srcb = alter_subreg (set_srcb);
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dest1 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 0 : 2));
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dest2 = gen_rtx_REG (DFmode,
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REGNO (set_dest) + (WORDS_BIG_ENDIAN ? 2 : 0));
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srca1 = gen_rtx_REG (DFmode,
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REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 0 : 2));
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srca2 = gen_rtx_REG (DFmode,
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REGNO (set_srca) + (WORDS_BIG_ENDIAN ? 2 : 0));
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srcb1 = gen_rtx_REG (DFmode,
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REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 0 : 2));
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srcb2 = gen_rtx_REG (DFmode,
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REGNO (set_srcb) + (WORDS_BIG_ENDIAN ? 2 : 0));
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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srca1 = gen_df_reg (set_srca, 0);
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srca2 = gen_df_reg (set_srca, 1);
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srcb1 = gen_df_reg (set_srcb, 0);
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srcb2 = gen_df_reg (set_srcb, 1);
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/* Now emit using the real source and destination we found, swapping
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the order if we detect overlap. */
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