Implement support for AArch64 Crypto PMULL.64.
gcc/ * config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins): Define builtin types for poly64_t poly128_t. (TYPES_BINOPP, aarch64_types_binopp_qualifiers): New. * aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi, aarch64_crypto_pmullv2di): New. * config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for poly64x2_t mangler. * config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define. (vmull_p64, vmull_high_p64): New. * config/aarch64/iterators.md (UNSPEC_PMULL<2>): New. testsuite/ * gcc.target/aarch64/pmull_1.c: New. From-SVN: r206120
This commit is contained in:
Tejas Belagod
Tejas Belagod
parent
b9cb0a44c1
commit
7baa225d39
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@ -1,3 +1,17 @@
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o2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
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Define builtin types for poly64_t poly128_t.
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(TYPES_BINOPP, aarch64_types_binopp_qualifiers): New.
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* aarch64/aarch64-simd-builtins.def: Update builtins table.
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* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi,
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aarch64_crypto_pmullv2di): New.
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* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for
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poly64x2_t mangler.
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* config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define.
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(vmull_p64, vmull_high_p64): New.
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* config/aarch64/iterators.md (UNSPEC_PMULL<2>): New.
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2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
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@ -156,6 +156,11 @@ static enum aarch64_type_qualifiers
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aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
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#define TYPES_BINOPU (aarch64_types_binopu_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_poly, qualifier_poly, qualifier_poly };
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#define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
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@ -574,6 +579,8 @@ aarch64_init_simd_builtins (void)
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/* Poly scalar type nodes. */
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tree aarch64_simd_polyQI_type_node = aarch64_build_poly_type (QImode);
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tree aarch64_simd_polyHI_type_node = aarch64_build_poly_type (HImode);
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tree aarch64_simd_polyDI_type_node = aarch64_build_poly_type (DImode);
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tree aarch64_simd_polyTI_type_node = aarch64_build_poly_type (TImode);
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/* Float type nodes. */
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tree aarch64_simd_float_type_node = aarch64_build_signed_type (SFmode);
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@ -598,6 +605,10 @@ aarch64_init_simd_builtins (void)
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"__builtin_aarch64_simd_poly8");
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(*lang_hooks.types.register_builtin_type) (aarch64_simd_polyHI_type_node,
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"__builtin_aarch64_simd_poly16");
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(*lang_hooks.types.register_builtin_type) (aarch64_simd_polyDI_type_node,
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"__builtin_aarch64_simd_poly64");
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(*lang_hooks.types.register_builtin_type) (aarch64_simd_polyTI_type_node,
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"__builtin_aarch64_simd_poly128");
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(*lang_hooks.types.register_builtin_type) (aarch64_simd_intTI_type_node,
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"__builtin_aarch64_simd_ti");
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(*lang_hooks.types.register_builtin_type) (aarch64_simd_intEI_type_node,
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@ -386,3 +386,7 @@
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VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
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VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
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VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
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/* Implemented by aarch64_crypto_pmull<mode>. */
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VAR1 (BINOPP, crypto_pmull, 0, di)
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VAR1 (BINOPP, crypto_pmull, 0, v2di)
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@ -4173,3 +4173,25 @@
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"sha256su1\\t%0.4s, %2.4s, %3.4s"
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[(set_attr "type" "crypto_sha256_slow")]
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)
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;; pmull
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(define_insn "aarch64_crypto_pmulldi"
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[(set (match_operand:TI 0 "register_operand" "=w")
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(unspec:TI [(match_operand:DI 1 "register_operand" "w")
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(match_operand:DI 2 "register_operand" "w")]
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UNSPEC_PMULL))]
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"TARGET_SIMD && TARGET_CRYPTO"
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"pmull\\t%0.1q, %1.1d, %2.1d"
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[(set_attr "type" "neon_mul_d_long")]
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)
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(define_insn "aarch64_crypto_pmullv2di"
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[(set (match_operand:TI 0 "register_operand" "=w")
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(unspec:TI [(match_operand:V2DI 1 "register_operand" "w")
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(match_operand:V2DI 2 "register_operand" "w")]
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UNSPEC_PMULL2))]
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"TARGET_SIMD && TARGET_CRYPTO"
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"pmull2\\t%0.1q, %1.2d, %2.2d"
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[(set_attr "type" "neon_mul_d_long")]
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)
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@ -6387,6 +6387,7 @@ static aarch64_simd_mangle_map_entry aarch64_simd_mangle_map[] = {
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{ V2DFmode, "__builtin_aarch64_simd_df", "13__Float64x2_t" },
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{ V16QImode, "__builtin_aarch64_simd_poly8", "12__Poly8x16_t" },
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{ V8HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x8_t" },
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{ V2DImode, "__builtin_aarch64_simd_poly64", "12__Poly64x2_t" },
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{ VOIDmode, NULL, NULL }
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};
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@ -75,6 +75,8 @@ typedef __builtin_aarch64_simd_poly8 poly8x16_t
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__attribute__ ((__vector_size__ (16)));
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typedef __builtin_aarch64_simd_poly16 poly16x8_t
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__attribute__ ((__vector_size__ (16)));
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typedef __builtin_aarch64_simd_poly64 poly64x2_t
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__attribute__ ((__vector_size__ (16)));
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typedef __builtin_aarch64_simd_uqi uint8x16_t
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__attribute__ ((__vector_size__ (16)));
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typedef __builtin_aarch64_simd_uhi uint16x8_t
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@ -88,6 +90,8 @@ typedef float float32_t;
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typedef double float64_t;
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typedef __builtin_aarch64_simd_poly8 poly8_t;
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typedef __builtin_aarch64_simd_poly16 poly16_t;
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typedef __builtin_aarch64_simd_poly64 poly64_t;
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typedef __builtin_aarch64_simd_poly128 poly128_t;
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typedef struct int8x8x2_t
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{
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@ -23014,6 +23018,19 @@ vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
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return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15);
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}
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static __inline poly128_t
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vmull_p64 (poly64_t a, poly64_t b)
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{
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return
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__builtin_aarch64_crypto_pmulldi_ppp (a, b);
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}
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static __inline poly128_t
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vmull_high_p64 (poly64x2_t a, poly64x2_t b)
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{
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return __builtin_aarch64_crypto_pmullv2di_ppp (a, b);
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}
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#endif
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/* vshl */
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@ -281,6 +281,8 @@
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UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
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UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
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UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
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UNSPEC_PMULL ; Used in aarch64-simd.md.
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UNSPEC_PMULL2 ; Used in aarch64-simd.md.
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])
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;; -------------------------------------------------------------------
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@ -1,3 +1,7 @@
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2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
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* gcc.target/aarch64/pmull_1.c: New.
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2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
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* gcc.target/aarch64/sha256_1.c: New.
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@ -0,0 +1,23 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+crypto" } */
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#include "arm_neon.h"
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poly128_t
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test_vmull_p64 (poly64_t a, poly64_t b)
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{
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return vmull_p64 (a, b);
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}
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/* { dg-final { scan-assembler-times "pmull\\tv" 1 } } */
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poly128_t
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test_vmull_high_p64 (poly64x2_t a, poly64x2_t b)
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{
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return vmull_high_p64 (a, b);
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}
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/* { dg-final { scan-assembler-times "pmull2\\tv" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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